ST7FLITE49K2T6TR STMicroelectronics, ST7FLITE49K2T6TR Datasheet - Page 65

• Manufacturer Part Number: ST7FLITE49K2T6TR
• Description: IC MCU 8BIT 8K FLASH 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE49K2T6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FLITE4x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• For Use With: 497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST7LITE49K2
9.4
Figure 26. Wait mode flowchart
1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
Active-halt and Halt modes
Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active-
Halt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following
table:
Table 20.
LTCSR TBIE
during the interrupt routine and cleared when the CC register is popped.
bit
0
0
0
1
x
Enabling/disabling Active-halt and Halt modes
ATCSR OVFIE
bit
0
1
1
x
x
WFI INSTRUCTION
N
ATCSRCK1 bit ATCSRCK0 bit
INTERRUPT
Y
x
x
1
x
0
OR SERVICE INTERRUPT
FETCH RESET VECTOR
256 CPU CLOCK CYCLE
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BIT
OSCILLATOR
PERIPHERALS
CPU
I BIT
N
DELAY
RESET
Y
0
1
1
x
x
OFF
OFF
X
ON
ON
ON
ON
ON
ON
ON
0
0
1)
Active-halt mode disabled
Active-halt mode enabled
Power saving modes
Meaning
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