ST7FLITE49K2T6TR STMicroelectronics, ST7FLITE49K2T6TR Datasheet - Page 43
![IC MCU 8BIT 8K FLASH 32LQFP](/photos/27/13/271337/tqfp-32_sml.jpg)
ST7FLITE49K2T6TR
Manufacturer Part Number
ST7FLITE49K2T6TR
Description
IC MCU 8BIT 8K FLASH 32LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITE49K2T6TR.pdf
(245 pages)
Specifications of ST7FLITE49K2T6TR
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
ST7FLITE4x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
I2C, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7FLI49M-D/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
For Use With
497-8399 - BOARD EVAL ST7LITE49M/STLED316S497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FLITE49K2T6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
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ST7LITE49K2
7.3
7.3.1
Note:
Table 6.
Reset sequence manager (RSM)
Introduction
The reset sequence manager includes three RESET sources as shown in
●
●
●
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
mapping.
The basic RESET sequence consists of 3 phases as shown in
●
●
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Active Phase depending on the RESET source
256 CPU clock cycle delay (see
Section 12.2.1 on page 189
ST7 clock sources
for further details.
Table
Hardware configuration
C
L1
EXTERNAL
SOURCE
OSC1
OSC1
OSC1
7)
CAPACITORS
LOAD
ST7
ST7
ST7
Supply, reset and clock management
OSC2
OSC2
OSC2
C
L2
Figure
14:
Figure
15:
43/245
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