ATMEGA128A-MU Atmel, ATMEGA128A-MU Datasheet - Page 63

• Manufacturer Part Number: ATMEGA128A-MU
• Description: MCU 8BIT 128K ISP FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.2
11.2.1
8151H–AVR–02/11
Register Description
MCUCR - MCU Control Register
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash
memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot
Loader section of the flash. The actual address of the start of the Boot Flash section is deter-
mined by the BOOTSZ fuses. Refer to the section
Self-Programming” on page 277
tables, a special write procedure must be followed to change the IVSEL bit:
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note:
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by
hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable
interrupts, as explained in the IVSEL description above. See Code Example below.
Bit
Read/Write
Initial Value
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If interrupt vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section
Write Self-Programming” on page 277
SRE
R/W
7
0
SRW10
R/W
6
0
for details. To avoid unintentional changes of interrupt vector
R/W
SE
5
0
for details on Boot Lock bits.
SM1
R/W
4
0
SM0
R/W
“Boot Loader Support – Read-While-Write
3
0
SM2
R/W
2
0
“Boot Loader Support – Read-While-
IVSEL
ATmega128A
R/W
1
0
IVCE
R/W
0
0
MCUCR
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