ATMEGA128A-MU Atmel, ATMEGA128A-MU Datasheet - Page 112

• Manufacturer Part Number: ATMEGA128A-MU
• Description: MCU 8BIT 128K ISP FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
15.1
15.1.1
15.2
8151H–AVR–02/11
Features
Overview
Restrictions in ATmega103 Compatibility Mode
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Note that in ATmega103 compatibility mode, only one 16-bit Timer/Counter is available
(Timer/Counter1). Also note that in ATmega103 compatibility mode, the Timer/Counter1 has two
Compare Registers (Compare A and Compare B) only.
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. Most register and bit references in this sec-
tion are written in general form. A lower case “n” replaces the Timer/Counter number, and a
lower case “x” replaces the Output Compare unit channel. However, when using the register or
bit defines in a program, the precise form must be used, that is, TCNT1 for accessing
Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in
placement of I/O pins, refer to
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-
tions are listed in the
True 16-bit Design (that is, allows 16-bit PWM)
Three Independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Ten Independent Interrupt Sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A, OCF3B,
OCF3C, and ICF3)
“Register Description” on page
“Pin Configurations” on page
134.
2. CPU accessible I/O Registers,
Figure
ATmega128A
15-1. For the actual
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