ATMEGA128A-MU Atmel, ATMEGA128A-MU Datasheet - Page 57

• Manufacturer Part Number: ATMEGA128A-MU
• Description: MCU 8BIT 128K ISP FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.6.2
8151H–AVR–02/11
WDTCR - Watchdog Timer Control Register
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-On Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the reset flags to identify a reset condition, the user should read and then reset
the MCUCSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the reset flags.
• Bits 7:5 – Reserved
These bits are reserved in the ATmega128A and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. In Safety Level 1 and 2, this bit
must also be set when changing the prescaler bits.
Configuration of the Watchdog Timer” on page 55.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm
described above.
Timer” on page 55.
• Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods
are shown in
Bit
Read/Write
Initial Value
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
ten to WDE even though it is set to one before the disable operation starts.
Table
R
7
–
0
See “Timed Sequences for Changing the Configuration of the Watchdog
10-2.
R
6
–
0
R
5
–
0
WDCE
R/W
4
0
WDE
R/W
See “Timed Sequences for Changing the
3
0
WDP2
R/W
2
0
WDP1
ATmega128A
R/W
1
0
WDP0
R/W
0
0
WDTCR
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