ATMEGA128A-MU Atmel, ATMEGA128A-MU Datasheet - Page 228
![MCU 8BIT 128K ISP FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128A-MU
Manufacturer Part Number
ATMEGA128A-MU
Description
MCU 8BIT 128K ISP FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
4KB
Ram Memory Size
4KB
Cpu Speed
16MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Price
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Manufacturer:
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21.9.3
21.9.4
8151H–AVR–02/11
TWSR - TWI Status Register
TWDR - TWI Data Register
• Bit 1 – Res: Reserved Bit
This bit is a reserved bit and will always read as zero.
• Bit 0 – TWIE: TWI Interrupt Enable
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti-
vated for as long as the TWINT flag is high.
• Bits 7:3 – TWS: TWI Status
These 5 bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different status
codes are described later in this section. Note that the value read from TWSR contains both the
5-bit status value and the 2-bit prescaler value. The application designer should mask the pres-
caler bits to zero when checking the Status bits. This makes status checking independent of
prescaler setting. This approach is used in this datasheet, unless otherwise noted.
• Bit 2 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bits 1:0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
Table 21-7.
To calculate bit rates, see
in the equation.
In Transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR
contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.
This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the Data Register
cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains sta-
ble as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
TWPS1
0
0
1
1
TWI Bit Rate Prescaler
TWS7
TWD7
R/W
R
7
1
7
1
TWS6
TWD6
R/W
“Bit Rate Generator Unit” on page
R
6
1
6
1
TWS5
TWD5
TWPS0
R/W
R
5
1
5
1
0
1
0
1
TWD4
TWS4
R/W
R
4
1
4
1
Prescaler Value
1
4
16
64
TWD3
TWS3
R/W
R
3
1
3
1
207. The value of TWPS1:0 is used
TWD2
R/W
R
2
–
0
2
1
TWPS1
TWD1
ATmega128A
R/W
R/W
1
0
1
1
TWPS0
TWD0
R/W
R/W
0
1
0
0
TWDR
TWSR
228
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