ATMEGA128A-MU Atmel, ATMEGA128A-MU Datasheet - Page 284

• Manufacturer Part Number: ATMEGA128A-MU
• Description: MCU 8BIT 128K ISP FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.8.3
25.8.4
25.8.5
25.8.6
25.8.7
8151H–AVR–02/11
Performing a Page Write
Using the SPM Interrupt
Consideration While Updating BLS
Prevent Reading the RWW Section During Self-Programming
Setting the Boot Loader Lock Bits by SPM
To execute page write, set up the address in the Z-pointer and RAMPZ, write “X0000101” to
SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and
R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must
be written zero during this operation.
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the
SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling
the SPMCSR Register in software. When using the SPM interrupt, the interrupt vectors should
be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is
blocked for reading. How to move the interrupts is described in
Special care must be taken if the user allows the Boot Loader section to be updated by leaving
Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the
entire Boot Loader, and further software updates might be impossible. If it is not necessary to
change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to
protect the Boot Loader software from any internal software changes.
During Self-Programming (either page erase or page write), the RWW section is always blocked
for reading. The user software itself must prevent that this section is addressed during the Self-
Programming operation. The RWWSB in the SPMCSR will be set as long as the RWW section is
busy. During Self-Programming the interrupt vector table should be moved to the BLS as
described in
RWW section after the programming is completed, the user software must clear the RWWSB by
writing the RWWSRE. See
an example.
To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR
and execute SPM within four clock cycles after writing SPMCSR. The only accessible lock bits
are the Boot Lock bits that may prevent the Application and Boot Loader section from any soft-
ware update by the MCU.
See
Flash access.
If bits 5:2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR.
The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to
load the Z-pointer with $0001 (same as used for reading the Lock bits). For future compatibility It
is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the lock-bits. When pro-
gramming the Lock Bits the entire Flash can be read during the operation.
Bit
R0
• Page Write to the RWW section: The NRWW section can be read during the page write.
• Page Write to the NRWW section: The CPU is halted during the operation.
Table 25-2
“Interrupts” on page
and
7
1
Table 25-3
6
1
“Simple Assembly Code Example for a Boot Loader” on page 286
for how the different settings of the Boot Loader Bits affect the
59, or the interrupts must be disabled. Before addressing the
BLB12
5
BLB11
4
BLB02
3
BLB01
“Interrupts” on page
2
ATmega128A
1
1
0
1
59.
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for