ATMEGA128A-MU Atmel, ATMEGA128A-MU Datasheet - Page 267

• Manufacturer Part Number: ATMEGA128A-MU
• Description: MCU 8BIT 128K ISP FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8151H–AVR–02/11
Table 24-5.
Signal
Name
HOLD
IREFEN
MUXEN_7
MUXEN_6
MUXEN_5
MUXEN_4
MUXEN_3
MUXEN_2
MUXEN_1
MUXEN_0
NEGSEL_2
NEGSEL_1
NEGSEL_0
PASSEN
PRECH
SCTEST
ST
VCCREN
Boundary-scan Signals for the ADC (Continued)
Direction
as Seen
from the
ADC
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Sample & Hold signal.
Sample analog signal
when low. Hold signal
when high. If gain stages
are used, this signal
must go active when
ACLK is high.
Enables Band-gap
reference as AREF
signal to DAC
Input Mux bit 7
Input Mux bit 6
Input Mux bit 5
Input Mux bit 4
Input Mux bit 3
Input Mux bit 2
Input Mux bit 1
Input Mux bit 0
Input Mux for negative
input for differential
signal, bit 2
Input Mux for negative
input for differential
signal, bit 1
Input Mux for negative
input for differential
signal, bit 0
Enable pass-gate of gain
stages.
Precharge output latch of
comparator. (Active low)
Switch-cap TEST
enable. Output from x10
gain stage send out to
Port Pin having ADC_4
Output of gain stages will
settle faster if this signal
is high first two ACLK
periods after AMPEN
goes high.
Selects Vcc as the ACC
reference voltage.
Recommen-
ded Input
when not
in Use
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
ATmega128A
Output Values when
Recommended Inputs
are Used, and CPU is
not Using the ADC
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
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