ATMEGA128A-MU Atmel, ATMEGA128A-MU Datasheet - Page 143

• Manufacturer Part Number: ATMEGA128A-MU
• Description: MCU 8BIT 128K ISP FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.11.19 TIFR - Timer/Counter Interrupt Flag Register
15.11.20 ETIFR - Extended Timer/Counter Interrupt Flag Register
8151H–AVR–02/11
Note:
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 flag is set when the coun-
ter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt vector is executed. Alternatively,
ICF1 can be cleared by writing a logic one to its bit location.
• Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register A (OCR1A).
Note that a forced output compare (FOC1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the Output Compare Match A interrupt vector is executed.
Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register B (OCR1B).
Note that a forced output compare (FOC1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the Output Compare Match B interrupt vector is executed.
Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 2 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In normal and CTC modes, the
TOV1 flag is set when the timer overflows. Refer to
behavior when using another WGMn3:0 bit setting.
• TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is
• Bit 7:6 – Reserved
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be set to zero when ETIFR is written.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
This register contains flag bits for several Timer/Counters, but only timer 1 bits are described in
this section. The remaining bits are described in their respective timer sections.
OCF2
R/W
R/W
7
0
7
–
0
TOV2
R/W
R/W
6
0
6
–
0
ICF3
ICF1
R/W
R/W
5
0
5
0
OCF3A
OCF1A
R/W
R/W
4
0
4
0
OCF3B
OCF1B
R/W
R/W
Table 15-5 on page 136
3
0
3
0
TOV3
TOV1
R/W
R/W
2
0
2
0
OCF3C
OCF0
ATmega128A
R/W
R/W
1
0
1
0
for the TOV1 flag
OCF1C
TOV0
R/W
R/W
0
0
0
0
ETIFR
TIFR
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