AT32UC3A1512-AUR Atmel, AT32UC3A1512-AUR Datasheet - Page 793
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AT32UC3A1512-AUR
Manufacturer Part Number
AT32UC3A1512-AUR
Description
MCU 32BIT 512KB FLASH 100-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A1512-AUR
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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41. Errata
41.1
41.1.1
41.1.2
41.1.3
32058J–AVR32–04/11
Rev. K
PWM
ADC
SPI
All industrial parts labelled with -UES (engineering samples) are revision E parts.
All automotive parts labelled with AT32UC3A0512-ALTRA or AT32UC3A0512-ALTTA are revi-
sion K parts.
1. PWM channel interrupt enabling triggers an interrupt
2. PWM counter restarts at 0x0001
3. PWM update period to a 0 value does not work
1. Sleep Mode activation needs additional A to D conversion
1. SPI Slave / PDCA transfer: no TX UNDERRUN flag
2. SPI FDIV option does not work
When enabling a PWM channel that is configured with center aligned period (CALG=1), an
interrupt is signalled.
Fix/Workaround
When using center aligned mode, enable the channel and read the status before channel
interrupt is enabled.
The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first
PWM period has one more clock cycle.
Fix/Workaround
- The first period is 0x0000, 0x0001, ..., period
- Consecutive periods are 0x0001, 0x0002, ..., period
It is impossible to update a period equal to 0 by the using the PWM update register
(PWM_CUPD).
Fix/Workaround
Do not update the PWM_CUPD register with a value equal to 0.
If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to
be informed of a character lost in transmission.
Fix/Workaround
For PDCA transfer: none.
Selecting clock signal using FDIV = 1 does not work as specified.
Fix/Workaround
Do not set FDIV = 1.
793
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