AT32UC3A1512-AUR Atmel, AT32UC3A1512-AUR Datasheet - Page 252
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AT32UC3A1512-AUR
Manufacturer Part Number
AT32UC3A1512-AUR
Description
MCU 32BIT 512KB FLASH 100-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A1512-AUR
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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24.14.7
Name:
Access:
Reset Value: 0x0000F009
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in
page 244
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last RHR read operation.
1 = A byte has been received in the RHR since the last read.
RXRDY behavior in Master mode can be seen in
RXRDY behavior in Slave mode can be seen in
page 244
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into THR register.
1 = As soon as a data byte is transferred from THR to internal shifter or if a NACK error is detected, TXRDY is set at the
same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in
32058J-AVR32-04/11
TXBUFE
31
23
15
–
–
7
–
and
and
TWI Status Register
SR
Read-only
Figure 24-29 on page
Figure 24-29 on page
RXBUFF
OVRE
30
22
14
–
–
6
ENDTX
GACC
244.
244.
29
21
13
–
–
5
Figure 24-8 on page
Figure 24-10 on page
Figure 24-24 on page
ENDRX
SVACC
Figure 24-26 on page
Figure 24-8 on page 225
28
20
12
–
–
4
EOSACC
SVREAD
27
19
11
–
–
3
225.
226.
241,
242,
and in
Figure 24-27 on page
Figure 24-27 on page
SCLWS
TXRDY
26
18
10
–
–
2
Figure 24-10 on page
ARBLST
RXRDY
25
17
–
–
9
1
243,
243,
AT32UC3A
226.
Figure 24-28 on
Figure 24-28 on
TXCOMP
NACK
24
16
–
–
8
0
252
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