AT32UC3A1512-AUR Atmel, AT32UC3A1512-AUR Datasheet - Page 673

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AT32UC3A1512-AUR

Manufacturer Part Number
AT32UC3A1512-AUR
Description
MCU 32BIT 512KB FLASH 100-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3A1512-AUR

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A1512-AUR
Manufacturer:
Atmel
Quantity:
10 000
32. Pulse Width Modulation Controller (PWM)
32.1
32.2
32058J–AVR32–04/11
Features
Description
Rev: 1.3.0.1
The PWM macrocell controls several channels independently. Each channel controls one
square output waveform. Characteristics of the output waveform such as period, duty-cycle and
polarity are configurable through the user interface. Each channel selects and uses one of the
clocks provided by the clock generator. The clock generator provides several clocks resulting
from the division of the PWM macrocell master clock.
All PWM macrocell accesses are made through registers mapped on the peripheral bus.
Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a
double buffering system in order to prevent an unexpected output waveform while modifying the
period or the duty-cycle.
7 Channels
One 20-bit Counter Per Channel
Common Clock Generator Providing Thirteen Different Clocks
Independent Channels
– A Modulo n Counter Providing Eleven Clocks
– Two Independent Linear Dividers Working on Modulo n Counter Outputs
– Independent Enable Disable Command for Each Channel
– Independent Clock Selection for Each Channel
– Independent Period and Duty Cycle for Each Channel
– Double Buffering of Period or Duty Cycle for Each Channel
– Programmable Selection of The Output Waveform Polarity for Each Channel
– Programmable Center or Left Aligned Output Waveform for Each Channel
AT32UC3A
673

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