AT32UC3A1512-AUR Atmel, AT32UC3A1512-AUR Datasheet - Page 532

• Manufacturer Part Number: AT32UC3A1512-AUR
• Description: MCU 32BIT 512KB FLASH 100-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A1512-AUR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 30-5.
32058J–AVR32–04/11
0x0370 - 0x03FC
0x031C
0x032C
0x033C
0x034C
0x035C
0x036C
0x0320
0x0324
0x0328
0x0330
0x0334
0x0338
0x0340
0x0344
0x0348
0x0350
0x0354
0x0358
0x0360
0x0364
0x0368
Offset
USB PB Memory Map
Register
Device DMA Channel 1 Status Register
Device DMA Channel 2 Next Descriptor
Address Register
Device DMA Channel 2 HSB Address Register
Device DMA Channel 2 Control Register
Device DMA Channel 2 Status Register
Device DMA Channel 3 Next Descriptor
Address Register
Device DMA Channel 3 HSB Address Register
Device DMA Channel 3 Control Register
Device DMA Channel 3 Status Register
Device DMA Channel 4 Next Descriptor
Address Register
Device DMA Channel 4 HSB Address Register
Device DMA Channel 4 Control Register
Device DMA Channel 4 Status Register
Device DMA Channel 5 Next Descriptor
Address Register
Device DMA Channel 5 HSB Address Register
Device DMA Channel 5 Control Register
Device DMA Channel 5 Status Register
Device DMA Channel 6 Next Descriptor
Address Register
Device DMA Channel 6 HSB Address Register
Device DMA Channel 6 Control Register
Device DMA Channel 6 Status Register
Reserved
NEXTDESC
NEXTDESC
NEXTDESC
NEXTDESC
NEXTDESC
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
UDDMA1_
UDDMA2_
UDDMA2_
UDDMA2_
UDDMA2_
UDDMA3_
UDDMA3_
UDDMA3_
UDDMA3_
UDDMA4_
UDDMA4_
UDDMA4_
UDDMA4_
UDDMA5_
UDDMA5_
UDDMA5_
UDDMA5_
UDDMA6_
UDDMA6_
UDDMA6_
UDDMA6_
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
ADDR
ADDR
ADDR
ADDR
ADDR
Name
–
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Access
–
AT32UC3A
Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
–
532