AT32UC3A1512-AUR Atmel, AT32UC3A1512-AUR Datasheet - Page 682

• Manufacturer Part Number: AT32UC3A1512-AUR
• Description: MCU 32BIT 512KB FLASH 100-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A1512-AUR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

32058J–AVR32–04/11
Figure 32-6. Synchronized Period or Duty Cycle Update
To prevent overwriting the CUPDx by software, the user can use status events in order to syn-
chronize his software. Two methods are possible. In both, the user must enable the dedicated
interrupt in IER at PWM Controller level.
The first method (polling method) consists of reading the relevant status bit in ISR Register
according to the enabled channel(s). See
The second method uses an Interrupt Service Routine associated with the PWM channel.
Note:
Figure 32-7. Polling Method
Note:
Reading the ISR register automatically clears CHIDx flags.
Polarity and alignment can be modified only when the channel is disabled.
End of Cycle
Acknowledgement and clear previous register state
The last write has been taken into account
PWM_CPRDx
Update of the Period or Duty Cycle
Writing in PWM_CUPDx
PWM_CUPDx Value
Writing in CPD field
PWM_ISR Read
1
User's Writing
CHIDx = 1
Figure
YES
32-7.
PWM_CDTYx
0
PWM_CMRx. CPD
AT32UC3A
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