AT32UC3A1512-AUR Atmel, AT32UC3A1512-AUR Datasheet - Page 425

• Manufacturer Part Number: AT32UC3A1512-AUR
• Description: MCU 32BIT 512KB FLASH 100-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A1512-AUR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

28.8.1
Register Name:
Access Type:
Reset Value:
•
This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed.
Table 28-9.
32058J–AVR32–04/11
MODE: SDRAMC Command Mode
0
0
0
0
1
1
1
31
23
15
MODE
–
–
–
7
–
0
0
1
1
0
0
1
SDRAMC Mode Register
0
1
0
1
0
1
0
Description
Normal mode. Any access to the SDRAM is decoded normally.
The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle.
The SDRAM Controller issues an “All Banks Precharge” command when the SDRAM device is accessed
regardless of the cycle.
The SDRAM Controller issues a “Load Mode Register” command when the SDRAM device is accessed
regardless of the cycle. The command will load the CAS latency from the Configuration Register and every other
value set to 0 into the Mode Register.
The SDRAM Controller issues an “Auto-Refresh” Command when the SDRAM device is accessed regardless of
the cycle. Previously, an “All Banks Precharge” command must be issued.
The SDRAM Controller issues an extended load mode register command when the SDRAM device is accessed
regardless of the cycle. The command will load the PASR, DS and TCR from the Low Power Register and every
other value set to 0 into the Extended Mode Register.
Deep power-down mode. Enters deep power-down mode.
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
MR
Read/Write
0x00000000
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
MODE
25
17
–
–
9
–
1
AT32UC3A
24
16
–
–
8
–
0
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