AT32UC3A1512-AUR Atmel, AT32UC3A1512-AUR Datasheet - Page 721

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AT32UC3A1512-AUR

Manufacturer Part Number
AT32UC3A1512-AUR
Description
MCU 32BIT 512KB FLASH 100-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3A1512-AUR

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A1512-AUR
Manufacturer:
Atmel
Quantity:
10 000
34. Audio Bitstream DAC (ABDAC)
34.1
34.2
32058J–AVR32–04/11
Features
Description
Rev: 1.0.1.1
The Audio Bitstream DAC converts a 16-bit sample value to a digital bitstream with an average
value proportional to the sample value. Two channels are supported, making the Audio Bit-
stream DAC particularly suitable for stereo audio. Each channel has a pair of complementary
digital outputs, DACn and DACn_N, which can be connected to an external high input imped-
ance amplifier.
The Audio Bitstream DAC is compromised of two 3rd order Sigma Delta D/A converter with an
oversampling ratio of 128. The samples are upsampled with a 4th order Sinc interpolation filter
(Comb4) before being input to the Sigmal Delta Modulator. In order to compensate for the pass
band frequency response of the interpolation filter and flatten the overall frequency response,
the input to the interpolation filter is first filtered with a simple 3-tap FIR filter.The total frequency
response of the Equalization FIR filter and the interpolation filter is given in
733. The digital output bitstreams from the Sigma Delta Modulators should be low-pass filtered
to remove high frequency noise inserted by the Modulation process.
The output DACn and DACn_N should be as ideal as possible before filtering, to achieve the
best SNR quality. The output can be connected to a class D amplifier output stage, or it can be
low pass filtered and connected to a high input impedance amplifier. A simple 1st order or higher
low pass filter that filters all the frequencies above 50 kHz should be adequate.
Digital Stereo DAC
Oversampled D/A conversion architecture
Digital bitstream outputs
Parallel interface
Connected to DMA Controller for background transfer without CPU intervention
– Oversampling ratio fixed 128x
– FIR equalization filter
– Digital interpolation filter: Comb4
– 3rd Order Sigma-Delta D/A converters
AT32UC3A
Figure 34-2 on page
721

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