AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 382
![IC MCU AVR32 512K FLASH 64TQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
MURATA
Quantity:
11 450
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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- Download datasheet (11Mb)
22.7.2.11
32059K–03/2011
Management of control endpoints
•Special considerations for control endpoints
•STALL handshake and retry mechanism
•Overview
•Control write
If a SETUP packet is received into a control endpoint for which a STALL is requested, the
Received SETUP Interrupt (RXSTPI) bit in UESTAn is set and STALLRQ and STALLEDI are
cleared. The SETUP has to be ACKed.
This management simplifies the enumeration process management. If a command is not sup-
ported or contains an error, the user requests a STALL and can return to the main task, waiting
for the next SETUP request.
The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
STALLRQ bit is set and if there is no retry required.
A SETUP request is always ACKed. When a new SETUP packet is received, the RXSTPI is set,
but not the Received OUT Data Interrupt (RXOUTI) bit.
The FIFO Control (FIFOCON) bit in UECONn and the Read/Write Allowed (RWALL) bit in
UESTAn are irrelevant for control endpoints. The user shall therefore never use them on these
endpoints. When read, their value are always zero.
Control endpoints are managed using:
Figure 22-15 on page 383
ler will not necessarily send a NAK on the first IN token:
• The RXSTPI bit which is set when a new SETUP packet is received and which shall be
• The RXOUTI bit which is set when a new OUT packet is received and which shall be cleared
• The Transmitted IN Data Interrupt (TXINI) bit which is set when the current bank is ready to
• If the user knows the exact number of descriptor bytes that must be read, it can then
• Or it can read the bytes and wait for the NAKed IN Interrupt (NAKINI) which tells that all the
cleared by firmware to acknowledge the packet and to free the bank.
by firmware to acknowledge the packet and to free the bank.
accept a new IN packet and which shall be cleared by firmware to send the packet.
anticipate the status stage and send a zero-length packet after the next IN token.
bytes have been sent by the host and that the transaction is now in the status stage.
shows a control write transaction. During the status stage, the control-
AT32UC3B
382
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