AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 239
![IC MCU AVR32 512K FLASH 64TQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
MURATA
Quantity:
11 450
Part Number:
AT32UC3B0512-A2UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Figure 19-24. Read Access Ordered by a MASTER
19.13.5.2
Figure 19-25. Write Access Ordered by a Master
32059K–03/2011
EOSVACC
EOSVACC
SVREAD
SVREAD
TXRDY
SVACC
RXRDY
SVACC
NACK
TWD
TWD
Write Operation
S
S
ADR
ADR
TWI answers with a NACK
TWI answers with a NACK
SADR does not match,
SADR does not match,
Notes:
The write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address
is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in
this case).
Until a STOP or REPEATED START condition is detected, TWI stores the received data in the
RHR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 19-25 on page 239
Notes:
W
R
NA
NA
1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. TXRDY is reset when data has been transmitted from THR to the shift register and set when
1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. RXRDY is set when data has been transmitted from the shift register to the RHR and reset
DATA
DATA
this data has been acknowledged or non acknowledged.
when this data is read.
NA
NA
P/S/Sr
P/S/Sr
describes the Write operation.
Write THR
SADR
SADR
TWI answers with an ACK
TWI answers with an ACK
SADR matches,
SADR matches,
W A
R
SVREAD has to be taken into account only while SVACC is active
SVREAD has to be taken into account only while SVACC is active
A
DATA
DATA
A
A
Read RHR
ACK/NACK from the Master
A
A
DATA NA S/Sr
DATA
AT32UC3B
NA
S/Sr
Read RHR
239
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