AT32UC3B0512-A2UT Atmel, AT32UC3B0512-A2UT Datasheet - Page 381
![IC MCU AVR32 512K FLASH 64TQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT32UC3B0512-A2UT
Manufacturer Part Number
AT32UC3B0512-A2UT
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B0512-A2UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
44
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
44
Ram Memory Size
96KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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22.7.2.7
22.7.2.8
22.7.2.9
22.7.2.10
32059K–03/2011
Suspend and wake-up
Detach
Remote wake-up
STALL request
When an idle USB bus state has been detected for 3 ms, the controller set the Suspend (SUSP)
interrupt bit in UDINT. The user may then write a one to the FRZCLK bit to reduce power con-
sumption. The MCU can also enter the Idle or Frozen sleep mode to lower again power
consumption.
To recover from the Suspend mode, the user shall wait for the Wake-Up (WAKEUP) interrupt bit,
which is set when a non-idle event is detected, then write a zero to FRZCLK.
As the WAKEUP interrupt bit in UDINT is set when a non-idle event is detected, it can occur
whether the controller is in the Suspend mode or not. The SUSP and WAKEUP interrupts are
thus independent of each other except that one bit is cleared when the other is set.
The reset value of the DETACH bit is one.
It is possible to initiate a device re-enumeration simply by writing a one then a zero to DETACH.
DETACH acts on the pull-up connections of the D+ and D- pads. See
details.
The Remote Wake-Up request (also known as Upstream Resume) is the only one the device
may send on its own initiative, but the device should have beforehand been allowed to by a
DEVICE_REMOTE_WAKEUP request from the host.
For each endpoint, the STALL management is performed using:
To answer the next request with a STALL handshake, STALLRQ has to be set by writing a one
to the STALL Request Set (STALLRQS) bit. All following requests will be discarded (RXOUTI,
etc. will not be set) and handshaked with a STALL until the STALLRQ bit is cleared, what is
done when a new SETUP packet is received (for control endpoints) or when the STALL Request
Clear (STALLRQC) bit is written to one.
Each time a STALL handshake is sent, the STALLEDI bit is set by the USBB and the EPnINT
interrupt is set.
• First, the USBB must have detected a “Suspend” state on the bus, i.e. the Remote Wake-Up
• The user may then write a one to the Remote Wake-Up (RMWKUP) bit in UDCON to send an
• When the controller sends the upstream resume, the Upstream Resume (UPRSM) interrupt
• RMWKUP is cleared at the end of the upstream resume.
• If the controller detects a valid “End of Resume” signal from the host, the End of Resume
• The STALL Request (STALLRQ) bit in UECONn to initiate a STALL request.
• The STALLed Interrupt (STALLEDI) bit in UESTAn is set when a STALL handshake has been
request can only be sent after a SUSP interrupt has been set.
upstream resume to the host for a remote wake-up. This will automatically be done by the
controller after 5ms of inactivity on the USB bus.
is set and SUSP is cleared.
(EORSM) interrupt is set.
sent.
“Device mode”
AT32UC3B
for further
381
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