AT32UC3B064-Z2UR Atmel, AT32UC3B064-Z2UR Datasheet - Page 651
![MCU AVR32 64K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT32UC3B064-Z2UR
Manufacturer Part Number
AT32UC3B064-Z2UR
Description
MCU AVR32 64K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B064-Z2UR
Package / Case
64-QFN
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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31.1.2.3
32059J–12/2010
Power Manager
5. Module hangs when CSAAT=1 on CS0
6. Disabling SPI has no effect on flag TDRE flag
1. If the BOD level is higher than VDDCORE, the part is constantly under reset
2. When the main clock is RCSYS, TIMER_CLOCK5 is equal to PBA clock
3. VDDCORE power supply input needs to be 1.95V
4. Clock sources will not be stopped in STATIC sleep mode if the difference between
5. Increased Power Consunption in VDDIO in sleep modes
SPI Disable does not work in Slave mode.
Fix/workaround
Read the last received data then perform a Software reset.
SPI data transfer hangs with CSAAT=1 in CSR0 and MODFDIS=0 in MR. When CSAAT=1
in CSR0 and mode fault detection is enabled (MODFDIS=0 in MR), the SPI module will not
start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MODFDIS in MR.
Disabling SPI has no effect on TDRE whereas the write data command is filtered when SPI
is disabled. This means that as soon as the SPI is disabled it becomes impossible to reset
the TDRE flag by writing in the TDR. So if the SPI is disabled during a PDCA transfer, the
PDCA will continue to write data in the TDR (as TDRE stays high) until its buffer is empty,
and all data written after the disable command is lost.
Fix/Workaround
Disable the PDCA, 2 NOP (minimum), disable SPI. When you want to continue the transfer:
Enable SPI, enable PDCA.
If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will
be in constant reset.
Fix/Workaround
Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than
VDDCORE max and disable the BOD.
When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to PBA Clock
and not PBA Clock / 128.
Fix/workaround:
None.
When used in dual power supply, VDDCORE needs to be 1.95V.
Fix/workaround:
When used in single power supply, VDDCORE needs to be connected to VDDOUT, which is
configured on revision C at 1.95V (typ.).
CPU and PBx division factor is too big
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when going
to a sleep mode where the system RC oscillator is turned off, then high speed clock sources
will not be turned off. This will result in a significantly higher power consumption during the
sleep mode.
Fix/Workaround
Before going to sleep modes where the system RC oscillator is stopped, make sure that the
factor between the CPU/HSB and PBx frequencies is less than or equal to 4.
AT32UC3B
651
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