AT32UC3B064-Z2UR Atmel, AT32UC3B064-Z2UR Datasheet - Page 22
![MCU AVR32 64K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT32UC3B064-Z2UR
Manufacturer Part Number
AT32UC3B064-Z2UR
Description
MCU AVR32 64K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B064-Z2UR
Package / Case
64-QFN
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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6.4
6.4.1
6.4.2
32059J–12/2010
Programming Model
Register File Configuration
Status Register Configuration
The AVR32UC register file is shown below.
Figure 6-3.
The Status Register (SR) is split into two halfwords, one upper and one lower, see
page 22
code flags and the R, T, and L bits, while the upper halfword contains information about the
mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 6-4.
Application
Bit 31
Bit 31
SP_APP
INT0PC
INT1PC
FINTPC
SMPC
0
-
R12
R11
R10
PC
LR
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
LC
Bit 0
1
0
-
and
0
Supervisor
Bit 31
-
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
Figure 6-5 on page
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
The AVR32UC Register File
The Status Register High Halfword
0
-
Bit 0
DM
0
INT0
Bit 31
SP_SYS
D
0
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
0
-
M2
0
INT1
Bit 31
SP_SYS
FINTPC
23. The lower word contains the C, Z, N, V, and Q condition
INT0PC
INT1PC
SMPC
R12
R11
R10
M1
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
0
Bit 0
M0
1
INT2
Bit 31
EM
1
SP_SYS
FINTPC
INT0PC
INT1PC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
I3M
0
SS_STATUS
Bit 0
SS_SP_SYS
SS_SP_APP
SS_ADRR
SS_ADRF
SS_ADR0
SS_ADR1
SS_RAR
SS_RSR
I2M
FE
0
INT3
Bit 31
SP_SYS
INT0PC
INT1PC
FINTPC
I1M
SMPC
0
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
I0M
0
Bit 16
GM
Exception
Bit 31
1
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit name
Initial value
Global Interrupt Mask
Interrupt Level 0 Mask
Interrupt Level 1 Mask
Interrupt Level 2 Mask
Interrupt Level 3 Mask
Exception Mask
Mode Bit 0
Mode Bit 1
Mode Bit 2
Reserved
Debug State
Debug State Mask
Reserved
Bit 0
NMI
Bit 31
AT32UC3B
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
Figure 6-4 on
Secure
Bit 31
SP_SEC
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
22
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