AT32UC3B064-Z2UR Atmel, AT32UC3B064-Z2UR Datasheet - Page 241
![MCU AVR32 64K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT32UC3B064-Z2UR
Manufacturer Part Number
AT32UC3B064-Z2UR
Description
MCU AVR32 64K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B064-Z2UR
Package / Case
64-QFN
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Figure 19-24. Read Access Ordered by a MASTER
19.13.5.2
Figure 19-25. Write Access Ordered by a Master
32059J–12/2010
EOSVACC
EOSVACC
SVREAD
SVREAD
TXRDY
SVACC
RXRDY
SVACC
NACK
TWD
TWD
Write Operation
S
S
ADR
ADR
TWI answers with a NACK
TWI answers with a NACK
SADR does not match,
SADR does not match,
Notes:
The write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address
is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in
this case).
Until a STOP or REPEATED START condition is detected, TWI stores the received data in the
RHR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected,
SVACC is reset.
Figure 19-25 on page 241
Notes:
W
R
NA
NA
1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. TXRDY is reset when data has been transmitted from THR to the shift register and set when
1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. RXRDY is set when data has been transmitted from the shift register to the RHR and reset
DATA
DATA
this data has been acknowledged or non acknowledged.
when this data is read.
NA
NA
P/S/Sr
P/S/Sr
describes the Write operation.
Write THR
SADR
SADR
TWI answers with an ACK
TWI answers with an ACK
SADR matches,
SADR matches,
W A
R
SVREAD has to be taken into account only while SVACC is active
SVREAD has to be taken into account only while SVACC is active
A
DATA
DATA
A
A
Read RHR
ACK/NACK from the Master
A
A
DATA NA S/Sr
DATA
AT32UC3B
NA
S/Sr
Read RHR
241
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