AT32UC3B064-Z2UR Atmel, AT32UC3B064-Z2UR Datasheet - Page 102
![MCU AVR32 64K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT32UC3B064-Z2UR
Manufacturer Part Number
AT32UC3B064-Z2UR
Description
MCU AVR32 64K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B064-Z2UR
Package / Case
64-QFN
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 102 of 680
- Download datasheet (10Mb)
Figure 13-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge
13.6.3
13.6.4
32059J–12/2010
EXTINTn/NMI
FILTER off
FILTER on
ISR.INTn:
ISR.INTn:
CLK_SYNC
Non-Maskable Interrupt
Asynchronous Interrupts
The NMI supports the same features as the external interrupts, and is accessed through the
same registers. The description in
instead of the INTn bits.
The NMI is non-maskable within the CPU in the sense that it can interrupt any other execution
mode. Still, as for the other external interrupts, the actual NMI input can be enabled and disabled
by accessing the registers in the EIC.
Each external interrupt can be made asynchronous by writing a one to INTn in the ASYNC reg-
ister. This will route the interrupt signal through the asynchronous path of the module. All edge
interrupts will be interpreted as level interrupts and the filter is disabled. If an interrupt is config-
ured as edge triggered interrupt in asynchronous mode, a zero in EDGE.INTn will be interpreted
as low level, and a one in EDGE.INTn will be interpreted as high level.
EIC_WAKE will be set immediately after the source triggers the interrupt, while the correspond-
ing bit in ISR and the interrupt to the interrupt controller will be set on the next rising edge of
CLK_SYNC. Please refere to
When CLK_SYNC is stopped only asynchronous interrupts remain active, and any short spike
on this interrupt will wake up the device. EIC_WAKE will restart CLK_SYNC and ISR will be
updated on the first rising edge of CLK_SYNC.
Figure 13-4 on page 103
Section 13.6.1
should be followed, accessing the NMI bit
for details.
AT32UC3B
102
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