AT32UC3B064-Z2UR Atmel, AT32UC3B064-Z2UR Datasheet - Page 286
![MCU AVR32 64K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT32UC3B064-Z2UR
Manufacturer Part Number
AT32UC3B064-Z2UR
Description
MCU AVR32 64K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B064-Z2UR
Package / Case
64-QFN
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 286 of 680
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• CKG: Transmit Clock Gating Selection
• CKI: Transmit Clock Inversion
• CKO: Transmit Clock Output Mode Selection
• CKS: Transmit Clock Selection
32059J–12/2010
Others
CKG
CKO
CKS
CKI affects only the Transmit Clock and not the output clock signal.
1: The data outputs (Data and Frame Sync signals) are shifted out on transmit clock rising edge. The Frame sync signal input is
sampled on transmit clock falling edge.
0: The data outputs (Data and Frame Sync signals) are shifted out on transmit clock falling edge. The Frame sync signal input is
sampled on transmit clock rising edge.
0
1
2
3
0
1
2
3
0
1
2
None, continuous clock
Transmit Clock enabled only if TX_FRAME_SYNC is low
Transmit Clock enabled only if TX_FRAME_SYNC is high
Reserved
Selected Transmit Clock
Divided Clock
RX_CLOCK clock signal
TX_CLOCK Pin
Reserved
Transmit Clock Gating
Transmit Clock Output Mode
None
Continuous transmit clock
Transmit clock only during data transfers
Reserved
TX_CLOCK pin
Input-only
Output
Output
AT32UC3B
286
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