AT32UC3B064-Z2UR Atmel, AT32UC3B064-Z2UR Datasheet - Page 488
![MCU AVR32 64K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT32UC3B064-Z2UR
Manufacturer Part Number
AT32UC3B064-Z2UR
Description
MCU AVR32 64K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B064-Z2UR
Package / Case
64-QFN
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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23.6.1.5
32059J–12/2010
TC operating modes
• The clock can be enabled or disabled by the user by writing to the Counter Clock
• The clock can also be started or stopped: a trigger (software, synchro, external or compare)
Figure 23-3. Clock Control
Each channel can independently operate in two different modes:
• Capture mode provides measurement on signals.
• Waveform mode provides wave generation.
The TC operating mode selection is done by writing to the Wave bit in the CCRn register
(CCRn.WAVE).
In Capture mode, TIOA and TIOB are configured as inputs.
In Waveform mode, TIOA is always configured to be an output and TIOB is an output if it is not
selected to be the external trigger.
Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and
CCRn.CLKDIS). In Capture mode it can be disabled by an RB load event if the Counter Clock
Disable with RB Loading bit in CMRn is written to one (CMRn.LDBDIS). In Waveform mode, it
can be disabled by an RC Compare event if the Counter Clock Disable with RC Compare bit in
CMRn is written to one (CMRn.CPCDIS). When disabled, the start or the stop actions have no
effect: only a CLKEN command in CCRn can re-enable the clock. When the clock is enabled,
the Clock Enabling Status bit is set in SRn (SRn.CLKSTA).
always starts the clock. In Capture mode the clock can be stopped by an RB load event if the
Counter Clock Stopped with RB Loading bit in CMRn is written to one (CMRn.LDBSTOP). In
Waveform mode it can be stopped by an RC compare event if the Counter Clock Stopped with
RC Compare bit in CMRn is written to one (CMRn.CPCSTOP). The start and the stop
commands have effect only if the clock is enabled.
Selected
Clock
Counter
Clock
Q
S
R
Trigger
CLKSTA
Q
CLKEN
S
R
Event
Stop
CLKDIS
AT32UC3B
Disable
Event
488
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