ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 89

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.9.6
13.9.7
7701E–AVR–02/11
TIMSK0 – Timer/Counter 0 Interrupt Mask Register
TIFR0 – Timer/Counter 0 Interrupt Flag Register
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bit 2- OCIE0B: Timer/Counter 0 Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the status register is set, the timer/coun-
ter 0 compare match B interrupt is enabled. The corresponding interrupt is executed if a
compare match in timer/counter occurs, i.e., when the OCF0B bit is set in the timer/counter 0
interrupt flag register (TIFR0).
• Bit 1– OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the status register is set, the timer/coun-
ter 0 compare match A interrupt is enabled. The corresponding interrupt is executed if a
compare match in timer/counter 0 occurs, i.e., when the OCF0A bit is set in the timer/counter
0 interrupt flag register (TIFR0).
• Bit 0– TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the status register is set, the timer/counter
0 overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in
timer/counter 0 occurs, i.e., when the TOV0 bit is set in the timer/counter 0 interrupt flag regis-
ter (TIFR0).
• Bits 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bit 2– OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a compare match occurs between the timer/counter 0 and the data
in OCR0B, the output compare register 0 B. OCF0B is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logi-
cal one to the flag. When the I-bit in SREG, OCIE0B (timer/counter compare b match interrupt
enable), and OCF0B are set, the timer/counter compare match interrupt is executed.
• Bit 1– OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a compare match occurs between the timer/counter 0 and the data
in OCR0A, the output compare register 0 A. OCF0A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logi-
cal one to the flag. When the I-bit in SREG, OCIE0A (timer/counter 0 compare match interrupt
enable), and OCF0A are set, the timer/counter 0 compare match interrupt is executed.
Bit
0x39 (0x59)
Read/Write
Initial Value
Bit
0x38 (0x58)
Read/Write
Initial Value
R
R
7
–
0
7
–
0
R
6
–
0
R
6
–
0
Atmel ATtiny24/44/84 [Preliminary]
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
R
3
–
0
R
3
–
0
OCIE0B
OCF0B
R/W
R/W
2
0
2
0
OCIE0A
OCF0A
R/W
R/W
1
0
1
0
TOIE0
TOV0
R/W
R/W
0
0
0
0
TIMSK0
TIFR0
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