ATTINY44-20PU Atmel, ATTINY44-20PU Datasheet
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ATTINY44-20PU
Specifications of ATTINY44-20PU
Related parts for ATTINY44-20PU
ATTINY44-20PU Summary of contents
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... Industrial Temperature Range: -40°C to +85°C • Low Power Consumption – Active Mode (1 MHz System Clock): 300 µA @ 1.8V – Power-Down Mode: 0.1 µA @ 1.8V ® 8-Bit Microcontroller 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny24 ATtiny44 ATtiny84 Rev. 8006K–AVR–10/10 ...
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Pin Configurations Figure 1-1. Pinout ATtiny24/44/84 (PCINT8/XTAL1/CLKI) PB0 (PCINT9/XTAL2) PB1 (PCINT11/RESET/dW) PB3 (PCINT10/INT0/OC0A/CKOUT) PB2 (PCINT7/ICP/OC0B/ADC7) PA7 (PCINT6/OC1A/SDA/MOSI/DI/ADC6) PA6 (ADC4/USCK/SCL/T1/PCINT4) PA4 (ADC3/T0/PCINT3) PA3 (ADC2/AIN1/PCINT2) PA2 (ADC1/AIN0/PCINT1) PA1 (ADC0/AREF/PCINT0) PA0 NOTE Bottom pad should be soldered to ground. DNC: Do Not ...
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Port B also serves the functions of various special features of the ATtiny24/44/84 as listed in Section 10.2 “Alternate Port Functions” on page 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length ...
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Overview ATtiny24/44/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24/44/84 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize ...
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... The device is manufactured using Atmel’s high density non-volatile memory technology. The on- chip ISP Flash allows the Program memory to be re-programmed in-system through an SPI serial interface conventional non-volatile memory programmer on-chip boot code running on the AVR core ...
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... About 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation ...
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CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle ...
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...
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The Status Register is neither automatically stored when entering an interrupt routine, nor restored when returning from an interrupt. This must be handled by software. 4.3.1 SREG – AVR Status Register Bit 0x3F (0x5F) Read/Write Initial Value • Bit 7 ...
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General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
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Figure 4-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing ...
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Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. Figure 4-4 vard architecture and the fast access ...
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RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in the following example. Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter ...
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Memories This section describes the different memories in the ATtiny24/44/84. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny24/44/84 features an EEPROM Memory for data storage. All three ...
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When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter- nal data ...
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EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in tion, however, lets the user software detect when the next byte can be written. If the ...
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The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator fre- quency is within the requirements described in page 30. 5.3.6 Program Examples The following code examples show one assembly and one C function for erase, ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
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... Bit 0 – EEAR8: EEPROM Address This is the most significant EEPROM address bit of ATtiny84. In devices with less EEPROM, i.e. ATtiny24/ATtiny44, this bit is reserved and will always read zero. The initial value of the EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written before the EEPROM is accessed ...
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... Initial Value • Bit 7 – EEAR7: EEPROM Address This is the most significant EEPROM address bit of ATtiny44. In devices with less EEPROM, i.e. ATtiny24, this bit is reserved and will always read zero. The initial value of the EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written before the EEPROM is accessed. • ...
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Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 5-1. EEPM1 When EEPE is set ...
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GPIOR2 – General Purpose I/O Register 2 Bit 0x15 (0x35) Read/Write Initial Value 5.5.6 GPIOR1 – General Purpose I/O Register 1 Bit 0x14 (0x34) Read/Write Initial Value 5.5.7 GPIOR0 – General Purpose I/O Register 0 Bit 0x13 (0x33) Read/Write ...
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Clock System Figure 6-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ment and Sleep ...
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I/O Clock – clk I/O The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by ...
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External Clock To drive the device from an external clock source, CLKI should be driven as shown in on page “0000”. Figure 6-2. When this clock source is selected, start-up times are determined by the SUT Fuses as shown ...
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RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 20-2 on page By changing the OSCCAL register from SW, see page 30 possible to get a higher calibration accuracy than by ...
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Low-Frequency Crystal Oscillator To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by setting CKSEL fuses to ‘0110’. The crystal should be connected as shown in For ...
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Table 6-9. CKSEL3:1 100 101 110 111 Notes: The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by fuses CKSEL3:1 as shown in The CKSEL0 Fuse together with the ...
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Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is therefore the Internal Oscillator running at 8.0 MHz with longest start-up time and an initial system ...
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The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the Factory calibrated frequency as ...
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Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when ...
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Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, ...
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Analog Comparator can be powered down by setting the ACD bit in parator Control and Status Register” on page mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.2 ADC Noise Reduction Mode ...
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... Limitations BOD disable functionality has been implemented in the following devices, only: • ATtiny24, revision E, and newer • ATtiny44, revision D, and newer • ATtiny84, revision B, and newer Revisions are marked on the device package and can be located as follows: • Bottom side of packages 14P3 and 14S1 • ...
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Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always ...
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BODS and BODSE must be set to one. Second, within four clock cycles, BODS must be set to one and BODSE must be set to zero. The BODS bit is active three clock cycles after it is set. A ...
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Bit 2 – PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 1 – PRUSI: Power Reduction USI ...
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System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP ...
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Reset Sources The ATtiny24/44/84 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is ...
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External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see ate a reset, even if the clock is not running. Shorter pulses are ...
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Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t “Watchdog Timer” on page ...
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The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down. To prevent unintentional disabling of the Watchdog or unintentional change of time-out ...
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Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following ...
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Register Description 8.5.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 0x34 (0x54) Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved ...
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To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 8-2. WDE • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when ...
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Bits 5, 2:0 – WDP3:0: Watchdog Timer Prescaler and 0 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in ...
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Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny24/44/84. For a general explanation of the AVR interrupt handling, see page 12. 9.1 Interrupt Vectors The interrupt vectors of ATtiny24/44/84 are described in Table 9-1. ...
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Address Labels Code 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 ; 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 ... 9.2 External Interrupts The External Interrupts are triggered by the INT0 pin ...
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Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end ...
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Register Description 9.3.1 MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 0x35 (0x55) Read/Write Initial Value • Bits 1:0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 ...
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Bit 4 – PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7:0 ...
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PCMSK0 – Pin Change Mask Register 0 Bit 0x12 (0x32) Read/Write Initial Value • Bits 7:0 – PCINT7:0: Pin Change Enable Mask 7:0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If ...
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I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O Note: 10.1.1 Configuring the Pin Each port pin consists ...
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Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 10.1.3 Switching Between ...
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Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ...
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C Code Example unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTA = (1<<PA4)|(1<<PA1)|(1<<PA0); DDRA = (1<<DDA3)|(1<<DDA2)|(1<<DDA1)|(1<<DDA0); /* Insert nop for synchronization*/ _NOP(); /* Read port pins */ i ...
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Figure 10-5. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: The overriding signals may not be present in all port pins, but the ...
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Table 10-2 ure 10-5 in the modules having the alternate function. Table 10-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the ...
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Alternate Functions of Port A The Port A pins with alternate function are shown in Table 10-3. • Port A, Bit 0 – ADC0/AREF/PCINT0 • ADC0: Analog to Digital Converter, Channel 0 • AREF: External Analog Reference for ADC. ...
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Port A, Bit 1 – ADC1/AIN0/PCINT1 • ADC1: Analog to Digital Converter, Channel 1 • AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pull- up switched off to avoid the digital port function ...
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Port A, Bit 6 – ADC6/DI/SDA/MOSI/OC1A/PCINT6 • ADC6: Analog to Digital Converter, Channel 6 • SDA: Two-wire mode Serial Interface Data. • DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions, so ...
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Table 10-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 10-6. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny24/44/84 64 Overriding Signals for Alternate Functions in PA4:PA2 PA4/ADC4/USCK/SCL/T1/ ...
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Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-7. • Port B, Bit 0 – XTAL1/PCINT8 • XTAL1: Chip Clock Oscillator pin 1. Used for all chip clock sources except internal ...
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Port B, Bit 3 – RESET/dW/PCINT11 • RESET: External Reset input is active low and enabled by unprogramming (“1”) the RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as ...
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Table 10-9. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 1. 2. 10.3 Register Description 10.3.1 MCUCR – MCU Control Register Bit Read/Write Initial Value • Bit 6 – PUD: Pull-up Disable When this bit ...
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PINA – Port A Input Pins Bit 0x19 (0x39) Read/Write Initial Value 10.3.5 PORTB – Port B Data Register Bit 0x18 (0x38) Read/Write Initial Value 10.3.6 DDRB – Port B Data Direction Register Bit 0x17 (0x37) Read/Write Initial Value ...
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Timer/Counter0 with PWM 11.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period ...
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Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Inter- rupt Mask Register (TIMSK0). TIFR0 ...
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Figure 11-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...
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Figure 11-3 Figure 11-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble ...
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OCR0x value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting ...
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The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation, see 11.6.1 Compare Output Mode and Waveform ...
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The timing diagram for the CTC mode is shown in (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then coun- ter (TCNT0) is cleared. Figure 11-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt ...
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DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The ...
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COM0A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0x to toggle ...
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The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows ...
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Figure 11-8. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOVn Figure 11-9 on page 79 Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn TOVn Figure 11-10 ...
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Figure 11-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk I/O clk Tn (clk /8) I/O TCNTn (CTC) OCRnx OCFnx 11.9 Register Description 11.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x30 (0x50) Read/Write Initial Value ...
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Table 11-3. COM0A1 Note: Table 11-4 rect PWM mode. Table 11-4. COM0A1 Note: • Bits 5:4 – COM0B1, COM0B:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) ...
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Table 11-6 Table 11-6. COM0B1 Note: Table 11-7 rect PWM mode. Table 11-7. COM0B1 Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved in the ATtiny24/44/84 and will always ...
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Table 11-8. Mode Note: 11.9.2 TCCR0B – Timer/Counter Control Register B Bit 0x33 (0x53) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active ...
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A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved ...
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OCR0B – Output Compare Register B Bit 0x3C (0x5C) Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output ...
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When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed. • Bit 1 – OCF0A: Output Compare Flag 0 A The OCF0A bit is set ...
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Timer/Counter1 12.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on Compare ...
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Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines ...
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Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of 16-bit AVR Timer/Counters. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: • All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt ...
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Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con- taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower ...
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Figure 12-3. Input Capture Unit Block Diagram WRITE ICPn When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of ...
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Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin ...
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Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation A special feature of Output Compare unit ...
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The high byte (OCR1xH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the value ...
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Figure 12-5. Compare Match Output Unit, Schematic (non-PWM Mode) COMnx1 COMnx0 FOCnx clk I/O The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the COM1x1:0 bits are set. However, the ...
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Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The Compare Output mode ...
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Figure 12-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define ...
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High frequency allows physically small sized external components (coils, capaci- tors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum ...
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ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will ...
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The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution ...
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TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x update ...
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OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either ...
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Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively ...
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Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRnx OCFnx Figure 12-12 on page 104 using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. ...
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Figure 12-13. Timer/Counter Timing Diagram, with Prescaler (f (clk TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOVn and ICF n as TOP) OCRnx (Update at TOP) 12.10 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers ...
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Assembly Code Examples ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Examples unsigned int i; ... /* Set TCNT1 to 0x01FF */ ...
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C Code Example unsigned int TIM16_ReadTCNT1( void ) { } Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. The following code examples show how atomic write of the TCNT1 Register contents. ...
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C Code Example void TIM16_WriteTCNT1( unsigned int unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 TCNT1 = i; /* ...
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Table 12-2. COM1A1/COM1B1 Table 12-3 PWM mode. Table 12-3. COM1A1/COM1B1 Note: Table 12-4 correct or the phase and frequency correct, PWM mode. Table 12-4. COM1A1/COM1B1 Note: 8006K–AVR–10/10 Compare Output Mode, non-PWM COM1A0/COM1B0 ...
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Bits 1:0 – WGM11, WGM10: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- ...
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When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input ...
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FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear ...
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ICR1H and ICR1L – Input Capture Register 1 Bit 0x25 (0x45) 0x24 (0x44) Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the ...
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TIFR1 – Timer/Counter Interrupt Flag Register 1 Bit 0x0B (0x2B) Read/Write Initial Value • Bits 7:6 – Res: Reserved Bits These bits are reserved in the ATtiny24/44/84 and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, ...
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Timer/Counter Prescaler Timer/Counter0 and Timer/Counter1 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counters used as a general name The Timer/Counter can ...
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However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances recommended that maximum frequency of an external clock source is less than f ...
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USI – Universal Serial Interface 14.1 Features • Two-wire Synchronous Data Transfer (Master or Slave) • Three-wire Synchronous Data Transfer (Master or Slave) • Data Received Interrupt • Wakeup from Idle Mode • In Two-wire Mode: Wake-up from All ...
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The serial input is always sampled from the Data Input (DI) pin independent of the configuration. The 4-bit counter can be both read and written ...
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Figure 14-3. Three-wire Mode, Timing Diagram CYCLE USCK USCK DO DI The three-wire mode timing is shown in erence. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for ...
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SPITransfer_loop: The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored in register r16 prior to the function is ...
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SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ... SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (plus return). The code example assumes that the ...
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Figure 14-4. Two-wire Mode Operation, Simplified Diagram The data direction is not given by the physical layer. A protocol, like the one used by the TWI- bus, must be implemented to control the data flow. Figure 14-5. Two-wire Mode, Typical ...
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The master set the first bit to be transferred and releases the SCL line (C). The slave samples the data and shifts it into the USI Data Register at the positive edge of the SCL clock. 4. After eight ...
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Alternative USI Usage The flexible design of the USI allows used for other tasks when serial communication is not needed. Below are some examples. 14.4.1 Half-Duplex Asynchronous Data Transfer Using the USI Data Register in three-wire ...
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USIBR – USI Data Buffer Bit 0x10 (0x30) Read/Write Initial Value Instead of reading data from the USI Data Register the USI Buffer Register can be used. This makes controlling the USI less time critical and gives the CPU ...
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The 4-bit counter increments by one for each clock generated either by the external clock edge detector Timer/Counter0 Compare Match software using USICLK or USITC strobe bits. The clock source depends on the setting of the ...
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Table 14-1. USIWM1 Note: • Bits 3:2 – USICS1, USICS0: Clock Source Select These bits set the clock source for the USI Data Register and counter. The data output latch ensures that the output is changed ...
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Table 14-2 used for the USI Data Register and the 4-bit counter. Table 14-2. USICS1 • Bit 1 – USICLK: Clock Strobe Writing a one to this bit location strobes the USI Data ...
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Analog Comparator The analog comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator ...
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Table 15-1. ACME 15.2 Register Description 15.2.1 ACSR – Analog Comparator Control and Status Register Bit 0x08 (0x28) Read/Write Initial Value • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, ...
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Analog Comparator and the input capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture inter-rupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set. • Bits 1:0 – ACIS1, ACIS0: Analog ...
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Analog to Digital Converter 16.1 Features • 10-bit Resolution • 1.0 LSB Integral Non-linearity • ± 2 LSB Absolute Accuracy • 13µs Conversion Time • 15 kSPS at Maximum Resolution • Eight Multiplexed Single Ended Input Channels • Twelve ...
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Figure 16-1. Analog to Digital Converter Block Schematic AREF V CC ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 16.3 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approxi- mation. The minimum value ...
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If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input pair by the selected gain factor 20x, according to the setting of the MUX0 bit in ADMUX. This amplified value then ...
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Figure 16-2. ADC Auto Trigger Logic Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, con- stantly ...
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The ADC module contains a prescaler, as illustrated in ates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ...
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When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in Figure 16-6 this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional ...
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For a summary of conversion times, see Table 16-1. Condition First conversion Normal conversions Auto Triggered conversions Free Running conversion 16.6 Changing Channel or Reference Selection The MUX5:0 and REFS1:0 bits in the ADMUX Register are single buffered through a ...
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Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. 16.6.2 ADC Voltage Reference The reference voltage for the ADC (V ended channels that ...
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Figure 16-8. Analog Input Circuitry Note: 16.9 Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. When conversion accuracy is critical, the noise level can be reduced by applying ...
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Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 16-9. Offset Error Output Code • Gain Error: After adjusting for offset, the Gain Error is ...
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Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 16-11. Integral Non-linearity (INL) Output Code ...
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Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum ...
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MSB of the result (ADC9 in ADCH). If the bit is one, the result is negative, and if this bit is zero, the result is ...
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Register Description 16.13.1 ADMUX – ADC Multiplexer Selection Register Bit 0x07 (0x27) Read/Write Initial Value • Bits 7:6 – REFS1, REFS0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 16-3. REFS1 ...
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ADC, then changing multiplexer settings and then turn on the ADC. Alternatively, the first conversion results after changing multiplexer settings should be discarded. Table 16-4. Single Ended Input ADC0 (PA0) ADC1 (PA1) ADC2 (PA2) ...
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Table 16-5. Positive Differential Input ADC2 (PA2) ADC3 (PA3) ADC4 (PA4) ADC5 (PA5) ADC6 (PA6) ADC7 (PA7) 1. For offset calibration purpose the offset of the certain differential channels can be measure by selecting the same input for both negative ...
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Bit 6 – ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC ...
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ADCL and ADCH – ADC Data Register 16.13.3.1 ADLAR = 0 Bit 0x05 (0x25) 0x04 (0x24) Read/Write Initial Value 16.13.3.2 ADLAR = 1 Bit 0x05 (0x25) 0x04 (0x24) Read/Write Initial Value When an ADC conversion is complete, the result ...
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Bit 6 – ACME: Analog Comparator Multiplexer Enable See “ADCSRB – ADC Control and Status Register B” on page • Bit 5 – Res: Reserved Bit This is a reserved bit in ATtiny24/44/84. For compatibility with future devices always ...
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On-chip Debug System 17.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog , except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or ...
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When designing a system where debugWIRE will be used, the following must be observed: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the ...
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Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associ- ated protocol to read code and write (program) that code ...
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If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 18.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR ...
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EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation recommended ...
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To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit Rd Refer to To read the Fuse ...
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If successful, the contents of the destination register are as described in section ture Imprint Table” on page 18.7 Preventing Flash Corruption During periods of low V too low for the CPU and the Flash to operate properly. These issues ...
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Bit 5 – RSIG: Read Device Signature Imprint Table Issuing an LPM instruction within three cycles after RSIG and SPMEN bits have been set in SPMCSR will return the selected data (depending on Z-pointer value) from the device signature ...
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Memory Programming This section describes the different methods for programming ATtiny24/44/84 memories. 19.1 Program And Data Memory Lock Bits The ATtiny24/44/84 provides two lock bits which can be left unprogrammed (“1”) or can be pro- grammed (“0”) to obtain ...
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Fuse Bytes The ATtiny24/44/84 have three fuse bytes. describe the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table ...
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Table 19-5. Fuse Low Byte CKDIV8 CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Notes: Note that fuse bits are locked if Lock Bit 1 (LB1) is programmed. Fuse bits should be pro- grammed before lock bits. The status of fuse ...
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... Calibration bytes can also be read by the device firmware. See section Signature Data from Software” on page 19.4 Page Size Table 19-8. Device ATtiny24 ATtiny44 ATtiny84 Table 19-9. Device ATtiny24 ATtiny44 ATtiny84 ATtiny24/44/84 162 155. Device Signature Bytes Signature Byte 0 0x1E 0x1E 0x1E Table 19-6 on page 155. ...
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Serial Programming Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- put). See Figure 19-1. ...
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The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial ...
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Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO the end of the programming session, ...
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... Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See http://www.atmel.com/avr for Application Notes regarding programming and programmers. Figure 19-2. Serial Programming Instruction example ...
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If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out. Within the same page, the low data byte must be loaded ...
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High-Voltage Serial Programming Algorithm To program and verify the ATtiny24/44/84 in the High-voltage Serial Programming mode, the fol- lowing sequence is recommended (See instruction formats in 19.7.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in ...
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Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. • The command needs only be loaded once when writing or reading multiple memory locations. ...
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Figure 19-4. Addressing the Flash which is Organized in Pages PROGRAM MEMORY Figure 19-5. High-voltage Serial Programming Waveforms SDI PB0 SII PB1 SDO PB2 SCI PB3 19.7.5 Programming the EEPROM The EEPROM is organized in pages, see EEPROM, the data ...
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Reading the Flash The algorithm for reading the Flash memory is as follows (refer to 1. Load Command "Read Flash". 2. Read Flash Low and High Bytes. The contents at the selected address are available at serial output SDO. ...
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Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 (Continued) Instruction Instr.1/5 SDI 0_0000_0010_00 Load “Read Flash” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_bbbb_bbbb_00 SII 0_0000_1100_00 Read Flash SDO x_xxxx_xxxx_xx Low and High SDI 0_0000_0000_00 Bytes SII 0_0111_1000_00 SDO x_xxxx_xxxx_xx ...
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Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 (Continued) Instruction Instr.1/5 SDI 0_0010_0000_00 Write Lock SII 0_0100_1100_00 Bits SDO x_xxxx_xxxx_xx SDI 0_0000_0100_00 Read Fuse SII 0_0100_1100_00 Low Bits SDO x_xxxx_xxxx_xx SDI 0_0000_0100_00 Read Fuse SII 0_0100_1100_00 High Bits SDO ...
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Electrical Characteristics 20.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0. Voltage on RESET with respect to Ground......-0.5V to +13.0V ...
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Table 20-1. DC Characteristics. T Symbol Parameter (7) Power Supply Current I CC (8) Power-down mode Notes: 1. Typical values at +25°C. 2. “Min” means the lowest value where the pin is guaranteed to be read as high. 3. “Max” ...
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Figure 20-2. Maximum Frequency vs. V 20.4 Clock Characteristics 20.4.1 Accuracy of Calibrated Internal RC Oscillator It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on ...
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External Clock Drive Figure 20-3. External Clock Drive Waveform V IH1 V IL1 Table 20-3. External Clock Drive Characteristics Symbol Parameter 1/t Clock Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise ...
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... This implementation of power-on reset exists in newer versions of ATtiny24/44/84. The table below describes the characteristics of this power-on reset and it is valid for the following devices, only: • ATtiny24, revision E, and newer • ATtiny44, revision D, and newer • ATtiny84, revision B, and newer Table 20-6. Symbol ...
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Brown-Out Detection Table 20-7. Note: 20.6 Analog Comparator Characteristics Table 20-8. Analog Comparator Characteristics, T Symbol Parameter V Input Offset Voltage AIO I Input Leakage Current LAC Analog Propagation Delay (from saturation to slight overdrive) t APD Analog Propagation ...
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ADC Characteristics Table 20-9. ADC Characteristics, Single Ended Channels -40°C to +85°C Symbol Parameter Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Differential Non-linearity ...
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Table 20-10. ADC Characteristics, Differential Channels (Unipolar Mode), T Symbol Parameter Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain Error Offset Error Conversion Time Clock Frequency ...
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Table 20-11. ADC Characteristics, Differential Channels (Bipolar Mode), T Symbol Parameter Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain Error Offset Error Conversion Time Clock Frequency ...
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Serial Programming Characteristics Figure 20-4. Serial Programming Timing Figure 20-5. Serial Programming Waveform SERIAL DATA INPUT SERIAL DATA OUTPUT SERIAL CLOCK INPUT Table 20-12. Serial Programming Characteristics, T Symbol 1/t CLCL t CLCL 1/t CLCL t CLCL t SHSL ...
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High-Voltage Serial Programming Characteristics Figure 20-6. High-voltage Serial Programming Timing SDI (PA6), SII (PA5) Table 20-13. High-voltage Serial Programming Characteristics Symbol t SHSL t SLSH t IVSH t SHIX t SHOV t WLWH_PFB ATtiny24/44/84 184 t IVSH SCI (PB0) ...
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Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indica- tions of how the part will ...
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Table 21-2. PRR bit PRTIM1 PRTIM0 PRUSI PRADC 21.1.1 Example Calculate the expected current consumption in idle mode with USI, TIMER0, and ADC enabled 2.0V and f = 1MHz. From CC add 6.1% for the USI, 10.4% ...
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Figure 21-2. Active Supply Current vs. frequency ( MHz) Figure 21-3. Active Supply Current vs. V 8006K–AVR–10/10 ACTIVE SUPPLY CURRENT vs. FREQUENCY Frequency (MHz) (Internal ...
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Figure 21-4. Active Supply Current vs. V Figure 21-5. Active Supply Current vs. V ATtiny24/44/84 188 (Internal RC Oscillator, 1 MHz) CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 1.2 1 0.8 0.6 0.4 0.2 0 1.5 ...
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Idle Supply Current Figure 21-6. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) Figure 21-7. Idle Supply Current vs. Frequency ( MHz) 8006K–AVR–10/10 IDLE SUPPLY CURRENT vs. LOW FREQUENCY (PRR=0xFF) 0.18 0.16 0.14 0.12 0.1 ...
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Figure 21-8. Idle Supply Current vs. V Figure 21-9. Idle Supply Current vs. V ATtiny24/44/84 190 (Internal RC Oscillator, 8 MHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 2 1.8 1.6 1.4 1.2 1 0.8 0.6 ...
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Figure 21-10. Idle Supply Current vs. V 21.4 Power-down Supply Current Figure 21-11. Power-down Supply Current vs. V 8006K–AVR–10/10 (Internal RC Oscillator, 128 kHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 128 KHz 0.03 0.025 0.02 0.015 0.01 ...
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Figure 21-12. Power-down Supply Current vs. V 21.5 Standby Supply Current Figure 21-13. Standby Supply Current vs. V ATtiny24/44/84 192 POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 1.5 ...
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Pin Pull-up Figure 21-14. I/O pin Pull-up Resistor Current vs. Input Voltage (V Figure 21-15. I/O Pin Pull-up Resistor Current vs. input Voltage (V 8006K–AVR–10/10 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ...
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Figure 21-16. I/O pin Pull-up Resistor Current vs. Input Voltage (V Figure 21-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V ATtiny24/44/84 194 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE V 160 140 120 100 ...
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Figure 21-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V Figure 21-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 8006K–AVR–10/10 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 0.5 ...
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Pin Driver Strength Figure 21-20. I/O Pin Output Voltage vs. Sink Current (V Figure 21-21. I/O pin Output Voltage vs. Sink Current (V ATtiny24/44/84 196 I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT V 1 0.9 0.8 0.7 0.6 0.5 ...
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Figure 21-22. I/O Pin Output Voltage vs. Source Current (V Figure 21-23. I/O Pin output Voltage vs. Source Current (V 8006K–AVR–10/10 I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT V 3.5 3 2.5 2 1 ...
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Figure 21-24. Reset Pin Output Voltage vs. Sink Current (V Figure 21-25. Reset Pin Output Voltage vs. Sink Current (V ATtiny24/44/84 198 RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT V CC 1 0.5 1 ...
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Figure 21-26. Reset Pin Output Voltage vs. Source Current (V Figure 21-27. Reset Pin Output Voltage vs. Source Current (V 8006K–AVR–10/10 RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 3.5 3 2.5 2 1 0.5 ...
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Pin Threshold and Hysteresis Figure 21-28. I/O Pin Input Threshold Voltage vs. V Figure 21-29. I/O Pin Input threshold Voltage vs. V ATtiny24/44/84 200 I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' 3.5 3 ...