ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 110

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.10 Timer/Counter Timing Diagrams
110
Atmel ATtiny24/44/84 [Preliminary]
When changing the top value, the program must ensure that the new top value is higher or
equal to the value of all of the compare registers. If the top value is lower than any of the com-
pare registers, a compare match will never occur between TCNT1 and OCR1x.
As
mode, symmetrical in all periods. Since the OCR1x registers are updated at bottom, the length
of the rising and the falling slopes will always be equal. This gives symmetrical output pulses,
and is, therefore, frequency correct.
Using the ICR1 register for defining top works well when using fixed top values. By using
ICR1, the OCR1A register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is actively changed by changing the top value, using the OCR1A
as top is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM
waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted
PWM, and an inverted PWM output can be generated by setting the COM1x1:0 to three (see
Table 14-3 on page
direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by
setting (or clearing) the OC1x register at the compare match between OCR1x and TCNT1
when the counter increments, and clearing (or setting) the OC1x register at compare match
between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the out-
put when using phase and frequency correct PWM can be calculated by the following
equation:
The variable N represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x register represent special cases when generating a PWM
waveform output in the phase and frequency correct PWM mode. If the OCR1x is set equal to
bottom the output will be continuously low, and if set equal to top, the output will be set to high
for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The timer/counter is a synchronous design, and the timer clock (clkT1) is, therefore, shown as
a clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCR1x register is updated with the OCR1x buffer value (only for
modes utilizing double buffering).
setting of OCF1x.
f
OCnxPFCPWM
Figure 14-9 on page 109
=
---------------------------------
2
114). The actual OC1x value will only be visible on the port pin if the data
f
clk_I/O
N
TOP
shows, the output generated is, in contrast to the phase correct
Figure 14-10 on page 111
shows a timing diagram for the
7701E–AVR–02/11