ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 32

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.10
7.10.1
7.10.2
32
Register Description
Atmel ATtiny24/44/84 [Preliminary]
Oscillator Calibration Register – OSCCAL
Clock Prescaler Register – CLKPR
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. A pre-programmed calibration value
is automatically written to this register during chip reset, giving the Factory calibrated fre-
quency as specified in
register to change the oscillator frequency. The oscillator can be calibrated to frequencies as
specified in
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to
more than 8.8MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to logical zero
gives the lowest frequency range, setting this bit to logical one gives the highest frequency
range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F
gives a higher frequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in
the range.
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logical one to enable change of the CLKPS bits. The CLK-
PCE bit is only updated when the other bits in CLKPR are simultaneously written to logical
zero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are
written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out
period nor clear the CLKPCE bit.
• Bits 6..4 – Res: Reserved Bits
These bits are reserved bits in the Atmel
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal sys-
tem clock. These bits can be written at run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the speed
of all synchronous peripherals is reduced when a division factor is used. The division factors
are given in
Bit
0x31 (0x51)
Read/Write
Initial Value
Bit
0x26 (0x46)
Read/Write
Initial Value
Table 22-2 on page
Table 7-10 on page
CLKPCE
CAL7
R/W
R/W
7
7
0
CAL6
Table 22-2 on page
R/W
6
R
6
–
0
180. Calibration outside that range is not guaranteed.
Device Specific Calibration Value
33.
CAL5
R/W
5
R
5
–
0
®
CAL4
ATtiny24/44/84 and will always read as zero.
R/W
4
R
4
–
0
180. The application software can write this
CLKPS3
CAL3
R/W
R/W
3
3
CLKPS2
CAL2
See Bit Description
R/W
R/W
2
2
CLKPS1
CAL1
R/W
R/W
1
1
CLKPS0
CAL0
R/W
R/W
0
0
7701E–AVR–02/11
OSCCAL
CLKPR