ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 144

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.7
18.7.1
144
ADC Noise Canceller
Atmel ATtiny24/44/84 [Preliminary]
Analog Input Circuitry
The ADC features a noise canceller that enables conversion during sleep mode to reduce
noise induced from the CPU core and other I/O peripherals. The noise canceller can be used
with ADC noise reduction and idle modes. To make use of this feature, the following proce-
dure should be used:
Note that the ADC will not be automatically turned off when entering sleep modes other than
idle mode or ADC noise reduction mode. The user is advised to write logical zero to ADEN
before entering such sleep modes to avoid excessive power consumption.
The analog input circuitry for single-ended channels is illustrated in
An analog source applied to ADCn is subjected to the pin capacitance and input leakage of
that pin, regardless of whether that channel is selected as input for the ADC or not. When the
channel is selected, the source must drive the S/H capacitor through the series resistance
(combined resistance in the input path).
The ADC is optimized for analog signals with an output impedance of approximately 10k or
less. If such a source is used, the sampling time will be negligible. If a source with higher
impedance is used, the sampling time will depend on how long the source needs to charge the
S/H capacitor, with can vary widely. The user is recommended to only use low impedant
sources with slowly varying signals, since this minimizes the required charge transfer to the
S/H capacitor.
Signal components higher than the Nyquist frequency (f
distortion from unpredictable signal convolution. The user is advised to remove high-frequency
components with a low-pass filter before applying the signals as inputs to the ADC.
a. Make sure that the ADC is enabled and is not busy converting. Single-conversion
b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion
c. If no other interrupts occur before the ADC conversion completes, the ADC inter-
mode must be selected and the ADC conversion complete interrupt must be
enabled.
once the CPU has been halted.
rupt will wake up the CPU and execute the ADC conversion complete interrupt
routine. If another interrupt wakes up the CPU before the ADC conversion is com-
plete, that interrupt will be executed, and an ADC conversion complete interrupt
request will be generated when the ADC conversion completes. The CPU will
remain in active mode until a new sleep command is executed.
ADC/2
) should not be present to avoid
Figure 18-8 on page
7701E–AVR–02/11
145.