ATTINY24A-SSUR Atmel, ATTINY24A-SSUR Datasheet - Page 82

• Manufacturer Part Number: ATTINY24A-SSUR
• Description: MCU AVR 2KB FLASH 20MHZ 14SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24A-SSUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Package: 14SOIC W
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 12
• Interface Type: SPI/USI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.9.2
82
ATtiny24A/44A/84A
TCCR0B – Timer/Counter Control Register B
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is
changed according to its COM0A[1:0] bits setting. Note that the FOC0A bit is implemented as a
strobe. Therefore it is the value present in the COM0A[1:0] bits that determines the effect of the
forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is
changed according to its COM0B[1:0] bits setting. Note that the FOC0B bit is implemented as a
strobe. Therefore it is the value present in the COM0B[1:0] bits that determines the effect of the
forced compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0B as TOP.
The FOC0B bit is always read as zero.
• Bits 5:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24A/44A/84A and will always read as zero.
• Bit 3 – WGM02: Waveform Generation Mode
See the description in the
• Bits 2:0 – CS0[2:0]: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 11-9.
Bit
0x33 (0x53)
Read/Write
Initial Value
CS02
0
0
0
0
CS01
0
0
1
1
Clock Select Bit Description
FOC0A
W
7
0
CS00
0
1
0
1
FOC0B
“TCCR0A – Timer/Counter Control Register A” on page
W
6
0
Description
No clock source (Timer/Counter stopped)
clk
clk
clk
I/O
I/O
I/O
/(No prescaling)
/8 (From prescaler)
/64 (From prescaler)
R
5
0
–
R
4
–
0
WGM02
R/W
3
0
CS02
R/W
2
0
CS01
R/W
1
0
CS00
R/W
0
0
8183C–AVR–03/11
79.
TCCR0B