ATTINY24A-SSUR Atmel, ATTINY24A-SSUR Datasheet - Page 70

• Manufacturer Part Number: ATTINY24A-SSUR
• Description: MCU AVR 2KB FLASH 20MHZ 14SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24A-SSUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Package: 14SOIC W
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 12
• Interface Type: SPI/USI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.5
70
Output Compare Unit
ATtiny24A/44A/84A
Figure 11-2.
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the Clock Select bits (CS0[2:0]). When no clock source is selected (CS0[2:0] = 0)
the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clk
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter
Control Register B (TCCR0B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare output OC0A. For more
details about advanced counting sequences and waveform generation, see
tion” on page
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the WGM0[1:0] bits. TOV0 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers
(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a
match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-
cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location. The Waveform Generator uses the match signal to generate an output according to
operating mode set by the WGM0[2:0] bits and Compare Output mode (COM0x[1:0]) bits. The
max and bottom signals are used by the Waveform Generator for handling the special cases of
the extreme values in some modes of operation. See
Figure 11-3 on page 71
count
direction
clear
clk
top
bottom
Tn
DATA BUS
T0
TCNTn
73.
is present or not. A CPU write overrides (has priority over) all counter clear or
Counter Unit Block Diagram
T0
shows a block diagram of the Output Compare unit.
). clk
Increment or decrement TCNT0 by 1.
Select between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
Signalize that TCNT0 has reached minimum value (zero).
T0
can be generated from an external or internal clock source,
direction
count
clear
bottom
Control Logic
top
“Modes of Operation” on page
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
T0
Detector
Edge
in the following.
“Modes of Opera-
8183C–AVR–03/11
73.
Tn