ATTINY24A-SSUR Atmel, ATTINY24A-SSUR Datasheet - Page 134

• Manufacturer Part Number: ATTINY24A-SSUR
• Description: MCU AVR 2KB FLASH 20MHZ 14SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24A-SSUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Package: 14SOIC W
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 12
• Interface Type: SPI/USI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

voltage. The ADC voltage reference is selected by writing the REFS[1:0] bits in the ADMUX reg-
ister. Alternatives are the V
supply pin, the AREF pin and the internal 1.1V voltage reference.
CC
The analog input channel and differential gain are selected by writing to the MUX bits in
ADMUX. Any of the ADC input pins can be selected as single ended inputs to the ADC. For dif-
ferential measurements all analog inputs next to each other can be selected as input pairs. In
addition, differential alternatives include any analog input paired with ADC3. All differential input
pairs are measured by ADC trough the differential gain amplifier.
If differential channels are selected, the differential gain stage amplifies the voltage difference
between the selected input pair by the selected gain factor, 1x or 20x. The gain is set using the
MUX0 bit in the ADMUX register. The amplified value then becomes the analog input to the
ADC. If single ended channels are used, the gain amplifier is bypassed altogether.
The offset of the differential channels can be measure by selecting the same input for both neg-
ative and positive input. Offset calibration can be done for ADC0, ADC3 and ADC7. When any of
these are selected as both positive and negative input to the differential gain amplifier, the
remaining offset in the gain stage and conversion circuitry can be measured directly as the result
of the conversion. This value can then be subtracted from subsequent conversions with the
same gain setting, effectively reducing the offset error to below 1 LSB.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADCSRB.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH, only. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the
data registers belongs to the same conversion. Once ADCL is read, ADC access to data regis-
ters is blocked. This means that if ADCL has been read, and a conversion completes before
ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH
is read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC
access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will
trigger even if the result is lost.
16.4
Starting a Conversion
Make sure the ADC is powered by clearing the ADC Power Reduction bit, PRADC, in the Power
Reduction Register, PRR (see
“PRR – Power Reduction Register” on page
37).
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be cleared by hardware
when the conversion is completed. If a different data channel is selected while a conversion is in
progress, the ADC will finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is
enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS
bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,
the ADC prescaler is reset and a conversion is started. This provides a method of starting con-
versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new
conversion will not be started. If another positive edge occurs on the trigger signal during con-
version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific
interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus
ATtiny24A/44A/84A
134
8183C–AVR–03/11