ATTINY24A-SSUR Atmel, ATTINY24A-SSUR Datasheet - Page 13

• Manufacturer Part Number: ATTINY24A-SSUR
• Description: MCU AVR 2KB FLASH 20MHZ 14SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24A-SSUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Package: 14SOIC W
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 12
• Interface Type: SPI/USI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.7.1
4.8
4.8.1
8183C–AVR–03/11
Register Description
Interrupt Response Time
SPH and SPL – Stack Pointer Register
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in the following example.
Note:
The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-
mum. After four clock cycles the Program Vector address for the actual interrupt handling routine
is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt
execution response time is increased by four clock cycles. This increase comes in addition to the
start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Read/Write
Initial Value
Initial Value
Assembly Code Example
C Code Example
sei
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
_SEI(); /* set Global Interrupt Enable */
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
See
; set Global Interrupt Enable
“Code Examples” on page
RAMEND
RAMEND
SP15
R/W
R/W
SP7
15
7
RAMEND
RAMEND
SP14
SP6
R/W
R/W
14
6
RAMEND
RAMEND
SP13
SP5
R/W
R/W
13
5
6.
RAMEND
RAMEND
SP12
SP4
R/W
R/W
12
4
RAMEND
RAMEND
SP11
SP3
R/W
R/W
11
3
ATtiny24A/44A/84A
RAMEND
RAMEND
SP10
SP2
R/W
R/W
10
2
RAMEND
RAMEND
SP9
SP1
R/W
R/W
9
1
RAMEND
RAMEND
R/W
R/W
SP8
SP0
8
0
SPH
SPL
13