M30833FJFP#U5 Renesas Electronics America, M30833FJFP#U5 Datasheet - Page 280

IC M32C/83 MCU FLASH 100QFP

M30833FJFP#U5

Manufacturer Part Number
M30833FJFP#U5
Description
IC M32C/83 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30833FJFP#U5

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R
R
M
e
E
3
. v
J
2
0
Figure 21.7 G2BCR1 Register
1
C
9
3 .
B
8 /
0
1
3
0
3
J
G
Group 2 Base Timer Control Register 1
b7
4
a
NOTES:
0 -
n
o r
3 .
b6
0
1
1. The base timer is reset two f
u
2. The PRP bit is valid when the RTP bit in the G2POCRi register is set to "1" (not used)
3. When starting the group 2 base timer, set the BTS bit to "1" after the BT2S bit in the BTSR register is
4. When starting the base timers in multiple groups simultaneously, use the BTSR register. Set the
, 1
3
p
register. (See Figure 21.13 for details on the G2PO0 register.) When the RST1 bit is set to "1", the
value of the G2POi register (i=1 to7), for the waveform generation function and communication
function, must be set to a smaller value than that of the G2PO0 register.
1
set to "0".
BTS bit to "0".
b5
0
2
(
M
0
b4
0
3
6
2
b3
0
C
Page 255
8 /
b2
, 3
b1
M
3
b0
2
C
f o
(b6 - b5)
8 /
Symbol
RST0
RST1
RST2
4
BTS
PRP
(b3)
Bit
3
8
Symbol
G2BCR1
) T
8
BT2
clock cycles after the base timer matches the value set in the G2PO0
Base Timer
Reset Cause
Select Bit 0
Base Timer
Reset Cause
Select Bit 1
Base Timer
Reset Cause
Select Bit 2
Reserved Bit
Base Timer
Start Bit
Reserved Bit
Parallel Real-Time
Port Function
Select Bit
Bit Name
(3, 4)
(2)
Address
0163
16
0 : The base timer is not reset by synchronizing
1 : The base timer is reset by synchronizing
0 : The base timer is not reset by a reset
1 : The base timer is reset by a reset request
Set to "0"
0 : Base timer is reset
1 : Base timer starts counting
Set to "0"
0 : RTP output mode
1 : Parallel RTP output mode
0 : The base timer is not reset by matching
1 : The base timer is reset by matching with
with the group 1 base timer reset
with the group 1 base timer reset
request from the communication function
from the communication function
with the G2PO0 register
the G2PO0 register
Function
After Reset
00
(1)
16
RW
RW
RW
RW
RW
RW
RW
RW
21. Intelligent I/O

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