M30833FJFP#U5 Renesas Electronics America, M30833FJFP#U5 Datasheet
M30833FJFP#U5
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M30833FJFP#U5 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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M32C/83 Group 16/ (M32C/83, M32C/83T) 32 Hardware Manual RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is ...
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Keep safety first in your circuit designs! Renesas Technology Corp. puts the maximum effort into making semiconductor products 1. better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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Introduction This hardware manual provides detailed information on the M32C/83 Group (M32C/83, M32C/83T) microcom- puters. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit ...
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M16C Family Documents The following documents were prepared for the M16C family. Document Short Sheet Data Sheet Hardware Manual Software Manual Application Note RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc. NOTES : ...
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Table of Contents Quick Reference by Address _____________________ B-1 1. Overview _____________________________________ 1 1.1 Applications ................................................................................................................ 1 1.2 Performance Overview .............................................................................................. 2 1.3 Block Diagram ............................................................................................................ 4 1.4 Product Information ................................................................................................... 5 1.5 Pin Assignment .......................................................................................................... 6 1.6 Pin Description ...
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Setting Processor Mode .......................................................................................... 48 6.2.1 Applying VSS to CNVSS Pin ............................................................................ 48 6.2.2 Applying VCC to CNVSS Pin ............................................................................ 48 7. Bus................................................................................... 52 7.1 Bus Settings ............................................................................................................. 52 7.1.1 Selecting External Address Bus ...................................................................... 53 7.1.2 Selecting External ...
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Interrupts___________________________________ 89 10.1 Types of Interrupts ................................................................................................. 89 10.2 Software Interrupts ................................................................................................ 89 10.2.1 Undefined Instruction Interrupt ..................................................................... 89 10.2.2 Overflow Interrupt ........................................................................................... 89 10.2.3 BRK Interrupt .................................................................................................. 89 10.2.4 BRK2 Interrupt ................................................................................................ 90 10.2.5 INT Instruction Interrupt ................................................................................. ...
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DMAC Transfer Cycles ......................................................................................... 123 12.3 Channel Priority and DMA Transfer Timing ....................................................... 123 13. DMAC II ___________________________________ 125 13.1 DMAC II Settings .................................................................................................. 125 13.1.1 RLVL Register................................................................................................ 125 13.1.2 DMAC II Index ................................................................................................ 127 13.1.3 Interrupt Control Register ...
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Clock Asynchronous Serial I/O (UART) Mode ................................................... 188 16.2.1 Bit Rate .......................................................................................................... 192 16.2.2 Selecting LSB First or MSB First ................................................................. 193 16.2.3 Serial Data Logic Inverse ............................................................................. 193 16.2.4 TxD and RxD I/O Polarity Inverse ................................................................ 194 16.3 ...
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D/A Converter ______________________________ 240 19. CRC Calculation ____________________________ 243 20. X/Y Conversion _____________________________ 245 21. Intelligent I/O_______________________________ 248 21.1 Base Timer ............................................................................................................ 264 21.2 Time Measurement Function (Group 0 and 1) ................................................... 269 21.3 Waveform Generation Function .......................................................................... 274 ...
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CAN0 Error Interrupt Mask Register (C0EIMKR Register) ...................... 341 22.1.14 CAN0 Error Interrupt Status Register (C0EISTR Register) ..................... 342 22.1.15 CAN0 Global Mask Register, CAN0 Local Mask Register A and CAN0 Local Mask Register B (C0GMRj (j=0 to4), C0LMARj ...
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CPU Rewrite Mode ............................................................................................... 394 25.3.1 Flash Memory Control Register 0 (FMR0 Register) ................................... 395 25.3.2 Status Register.............................................................................................. 397 25.3.3 Data Protect Function ................................................................................... 398 25.3.4 How to Enter and Exit CPU Rewrite Mode .................................................. 399 25.3.5 Software Commands ...
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INT Interrupt .................................................................................................. 468 27.6.4 Watchdog Timer Interrupt ............................................................................ 469 27.6.5 Changing Interrupt Control Register .......................................................... 469 27.6.6 Changing IIOiIR Register ( 11) .......................................................... 469 27.6.7 Changing RLVL Register .............................................................................. 469 27.7 DMAC .................................................................................................................... 470 ...
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Quick Reference by Address Address Register 0000 16 0001 16 0002 16 0003 16 0004 Processor Mode Register 0 (PM0) 16 0005 Processor Mode Register 1 (PM1) 16 0006 System Clock Control Register 0 (CM0) 16 0007 System Clock Control ...
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Quick Reference by Address Address Register 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 DMA0 Interrupt Control Register (DM0IC) 16 0069 Timer B5 Interrupt Control Register (TB5IC) 16 006A DMA2 Interrupt ...
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Quick Reference by Address Address Register 00C0 Group 0 Time Measurement Register 0 (G0TM0)/ 16 00C1 Group 0 Waveform Generation Register 0 (G0PO0) 16 00C2 Group 0 Time Measurement Register 1 (G0TM1)/ 16 00C3 Group 0 Waveform Generation Register 1 ...
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Quick Reference by Address Address Register 0120 16 Group 1 Base Timer Register (G1BT) 0121 16 0122 Group 1 Base Timer Control Register 0 (G1BCR0) 16 0123 Group 1 Base Timer Control Register 1 (G1BCR1) 16 0124 Group 1 Time ...
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Quick Reference by Address Address Register 0180 16 Group 3 Waveform Generation Register 0 (G3PO0) 0181 16 0182 16 Group 3 Waveform Generation Register 1 (G3PO1) 0183 16 0184 16 Group 3 Waveform Generation Register 2 (G3PO2) 0185 16 0186 ...
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Quick Reference by Address Address Register 01E0 CAN0 Message Slot Buffer 0 Standard ID0 (C0SLOT0_0) 16 01E1 CAN0 Message Slot Buffer 0 Standard ID1 (C0SLOT0_1) 16 01E2 CAN0 Message Slot Buffer 0 Extended ID0 (C0SLOT0_2) 16 01E3 CAN0 Message Slot ...
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Quick Reference by Address Address Register CAN0 Message Slot 9 Control Register (C0MCTL9)/ 0239 16 CAN0 Local Mask Register B Standard ID1 (C0LMBR1) CAN0 Message Slot 10 Control Register (C0MCTL10)/ 023A 16 CAN0 Local Mask Register B Extended ID0 (C0LMBR2) ...
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Quick Reference by Address Address Register 02F0 16 02F1 16 02F2 16 02F3 16 02F4 UART4 Special Mode Register 4 (U4SMR4) 16 02F5 UART4 Special Mode Register 3 (U4SMR3) 16 02F6 UART4 Special Mode Register 2 (U4SMR2) 16 02F7 UART4 ...
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Quick Reference by Address Address Register 0350 16 Timer B0 Register (TB0) 0351 16 0352 16 Timer B1 Register (TB1) 0353 16 0354 16 Timer B2 Register (TB2) 0355 16 0356 Timer A0 Mode Register (TA0MR) 16 0357 Timer A1 ...
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Quick Reference by Address Address Register 03A0 Function Select Register A8 (PS8) 16 03A1 Function Select Register A9 (PS9) 16 03A2 16 03A3 16 03A4 16 03A5 16 03A6 16 03A7 16 03A8 16 03A9 16 03AA 16 03AB 16 ...
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M32C/83 Group (M32C/83, M32C/83T) SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER 1. Overview The M32C/83 Group (M32C/83, M32C/83T) microcomputer is a single-chip control unit that utilizes high- performance silicon gate CMOS technology with the M32C/80 Series CPU core. The M32C/83 Group (M32C/83, M32C/83T) ...
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1.2 Performance Overview Tables 1.1 and 1.2 list performance overview of the M32C/83 Group (M32C/83, M32C/83T). ...
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Table 1.2 M32C/83 Group (M32C/83, M32C/83T) Performance (100-Pin Package) Characteristic CPU Basic Instructions Minimum Instruction Execution ...
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1.3 Block Diagram Figure 1.1 shows a block diagram of the M32C/83 Group (M32C/83, M32C/83T) microcomputer. ...
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1.4 Product Information Table 1.3 lists the product information. Figure 1.2 shows the product numbering system. ...
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1.5 Pin Assignment Figures 1.3 to 1.5 show pin assignments (top view ...
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Table 1.4 Pin Characteristics for 144-Pin Package Pin Interrupt Control Port No Pin Pin P9 1 ...
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Table 1.4 Pin Characteristics for 144-Pin Package (Continued) Pin Control Interrupt Port No Pin Pin 49 ...
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Table 1.4 Pin Characteristics for 144-Pin Package (Continued) Pin Control Interrupt Port Timer Pin No Pin ...
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AN0 / AN0 / ...
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...
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Table 1.5 Pin Characteristics for 100-Pin Package Package Control Interrupt Pin No Port Pin Pin FP ...
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Table 1.5 Pin Characteristics for 100-Pin Package (Continued) Package Control Interrupt Pin No Port Pin Pin ...
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1.6 Pin Description Table 1.6 Pin Description (100-Pin and 144-Pin Packages) Classsfication Symbol I/O Type Power ...
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Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued) Classsfication Symbol I/O Type Main Clock Input ...
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Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued) Classsfication Symbol I/O Type STxD0 to Serial ...
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Table 1.6 Pin Description (144-Pin Package only) (Continued) Classsfication Symbol I/O Type I/O Ports P0 to ...
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Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. A register bank comprises 8 ...
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2.1 General Registers 2.1.1 Data Registers (R0, R1, R2 and R3) R0, R1, R2 and R3 ...
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2.1.8.5 Register Bank Select Flag (B) The register bank 0 is selected when the B flag ...
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Memory Figure 3.1 shows a memory map of the M32C/83 group (M32C/83, M32C/83T). M32C/83 group ...
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Special Function Registers (SFR) Address 0000 16 0001 16 0002 16 0003 16 0004 Processor ...
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Address 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 ...
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Address 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 ...
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Address 0090 UART0 Transmit /NACK Interrupt Control Register 16 0091 UART1/UART4 Bus Conflict Detect Interrupt Control Register ...
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Address 00C0 16 Group 0 Time Measurement/Waveform Generating Register 0 00C1 16 00C2 16 Group 0 ...
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Address 00F0 Group 0 Data Compare Register 0 16 00F1 Group 0 Data Compare Register 1 16 ...
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Address 0120 16 Group 1 Base Timer Register 0121 16 0122 Group 1 Base Timer Control ...
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Address 0150 Group 2 Waveform Generating Control Register 0 16 0151 Group 2 Waveform Generating Control Register ...
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Address 0180 16 Group 3 Waveform Generating Register 0 0181 16 0182 16 Group 3 Waveform ...
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Address 01B0 16 01B1 16 01B2 16 01B3 16 01B4 16 01B5 16 01B6 16 01B7 16 ...
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Address 01E0 CAN0 Message Slot Buffer 0 Standard ID0 16 01E1 CAN0 Message Slot Buffer 0 ...
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Address 0210 16 CAN0 Slot Interrupt Mask Register 0211 16 0212 16 0213 16 0214 CAN0 Error ...
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Address CAN0 Message Slot 9 Control Register / 0239 16 CAN0 Local Mask Register B Standard ...
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Address 02C0 16 X0 Register Y0 Register 02C1 16 02C2 16 X1 Register Y1 Register 02C3 16 ...
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Address 02F0 16 02F1 16 02F2 16 02F3 16 02F4 UART4 Special Mode Register 4 16 ...
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Address 0320 16 0321 16 0322 16 0323 16 0324 UART3 Special Mode Register 4 16 0325 ...
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Address 0350 16 Timer B0 Register 0351 16 0352 16 Timer B1 Register 0353 16 0354 ...
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Address 0380 16 A/D0 Register 0 0381 16 0382 16 A/D0 Register 1 0383 16 0384 16 ...
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<144-pin package> Address 03A0 Function Select Register A8 16 03A1 Function Select Register A9 16 03A2 ...
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<144-pin package> Address 03D0 Port P14 Register 16 03D1 Port P15 Register 16 03D2 Port P14 Direction ...
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<100-pin package> Address ...
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<100-pin package> Address ...
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Reset Hardware reset, software reset, and watchdog timer reset are available to reset the microcomputer. 5.1 ...
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more X required Microprocessor (2) mode BYTE = “H” BCLK ...
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Table 5.1 Pin States while RESET Pin is Held "L" Pin Name CNV SS P0 Input port ...
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5.4 Internal Space Figure 5.3 shows CPU register states after reset. Refer to 4. SFR for SFR ...
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Processor Mode NOTE M32C/83T can be used in single-chip mode. M32C/83T cannot be used in ...
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Processor Mode Register NOTES: 1. Rewrite the PM0 ...
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Processor Mode Register NOTES: 1. Rewrite the ...
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Figure 6.3 Memory Map in Each Processor Mode ...
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Bus In memory expansion mode or microprocessor mode, some pins function as bus control pins ...
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7.1.1 Selecting External Address Bus The number of externally-output address bus, chip-select signals and chip-select-assigned address _____ ...
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Table 7.2 Processor Mode and Port Function Single- Processor Chip Mode Mode PM05 to Access CS1 ...
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7.2 Bus Control Signals required to access external devices are provided and software wait states are inserted ...
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Example 1: When the microcomputer accesses the external space j specified by another chip-select signal in ...
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7.2.3 Read and Write Signals When set to the 16-bit data bus, the PM02 bit in the ...
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7.2.4 Bus Timing Bus cycle for the internal ROM and internal RAM are basically one BCLK ...
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Table 7.5 Software Wait State and Bus Cycle External Space Bus Status SFR Internal ROM/RAM Separate Bus ...
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(1) Separate Bus with No Wait State BCLK Write Signal Read Signal Data Bus (2) Address ...
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(1) Separate Bus with 3 Wait States BCLK Write Signal Read Signal Data Bus (2) Address Bus ...
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7.2.5 ALE Signal The ALE signal latches an address of the multiplexed bus. Latch an address ...
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(1) Separate Bus with 2 Wait States 1st cycle BCLK ...
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Table 7.7 Microcomputer Status in a Hold State Item Oscillation _____ _____ RD Signal, WR Signal, ...
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Clock Generation Circuit 8.1 Types of Clock Generation Circuits Four circuits are incorporated to generate the ...
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Figure 8.1 Clock Generation Circuit Page ...
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System Clock Control Register NOTES: 1. Rewrite the ...
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System Clock Control Register ...
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Main Clock Division Register NOTES: 1. Rewrite the MCD register ...
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Oscillation Stop Detect Register NOTES: ...
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Count Source Prescaler Register NOTES: 1. Rewrite the CNT3 to ...
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PLL Control Register NOTES: 1. ...
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PLL Control Register NOTES: 1. Rewrite the PLC1 ...
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8.1.1 Main Clock Main clock oscillation circuit generates the main clock. The main clock becomes a ...
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8.1.2 Sub Clock Sub clock oscillation circuit generates the sub clock. The sub clock becomes a clock ...
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8.1.3 On-chip Oscillator Clock On-chip oscillator generates the on-chip oscillator clock. The 1MHz on-chip oscillator clock ...
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Figure 8.11 Switching Procedure from On-chip Oscillator Clock to Main Clock 8.1.4 PLL Clock The PLL frequency ...
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Microcomputer V CONT C1=220pF, C2=0.1 µF, R1=1 k Figure 8.12 External ...
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8.2 CPU Clock and BCLK The CPU operation clock is referred to as the CPU clock. The ...
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8.3.3 f C32 f is the sub clock divided by 32. f C32 available when the ...
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8.5.1 Normal Operation Mode The normal operation mode is further separated into six modes. In normal operation ...
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8.5.2 Wait Mode In wait mode, the CPU clock stops running. The CPU and watchdog timer, ...
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8.5.2.3 Pin Status in Wait Mode Table 8.6 lists pin states in wait mode. Table 8.6 Pin ...
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Table 8.7 Interrupts to Exit Wait Mode Interrupt _______ NMI Interrupt Available Serial I/O Interrupt Available ...
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(7) The oscillation stop detect function is used, set the CM20 bit in the CM2 register to ...
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All oscillation is stopped CM10=1 Stop mode Interrupt Stop mode CM10=1 (Note 2) NOTES: 1. See ...
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Figure 8.15 Status Transition Page ...
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Protection The protection function protects important registers from being easily overwritten when a program runs ...
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10. Interrupts 10.1 Types of Interrupts Figure 10.1 shows types of interrupts. Software (Non-Maskable Interrupt) Interrupt ...
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10.2.4 BRK2 Interrupt The BRK2 interrupt occurs when the BRK2 instruction is executed. Do not use this ...
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10.3.2 Peripheral Function Interrupt The peripheral function interrupt occurs when a request from the peripheral functions ...
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10.5.1 Fixed Vector Tables The fixed vector tables are allocated addresses FFFFDC tables. Refer to 25.2 Functions ...
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Table 10.2 Relocatable Vector Tables Interrupt Generated by (2) BRK Instruction Reserved Space A/D1 DMA0 DMA1 ...
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Table 10.2 Relocatable Vector Tables (Continued) Interrupt Generated by Bus Conflict Detect, Start Condition Detect, +156 to ...
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10.6 Interrupt Request Reception Software interrupts and special interrupts occur when conditions to generate an interrupt ...
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Interrupt Control Register NOTES: 1. The BCN0IC register shares an ...
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Interrupt Control Register NOTES: 1. When the 16-bit data ...
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Exit Priority Register NOTES: 1. The microcomputer exits stop or ...
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10.6.3 Interrupt Sequence The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine ...
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10.6.4 Interrupt Response Time Figure 10.6 shows an interrupt response time. Interrupt response time is the period ...
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Table 10.4 Interrupt Sequence Execution Time Interrupt Peripheral Function INT Instruction _______ NMI Watchdog Timer Undefined ...
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10.6.6 Saving a Register In the interrupt sequence, the FLG register and PC are saved to the ...
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10.6.8 Interrupt Priority If two or more interrupt requests are sampled at the same sampling points ...
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High Each Interrupt Priority Level A/D1 Converter DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 ...
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______ 10.7 INT Interrupt External input generates the INTi interrupt ( 5). The ...
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______ 10.8 NMI Interrupt ______ The NMI interrupt occurs when the signal applied to the P8 ______ ...
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10.10 Address Match Interrupt The address match interrupt occurs immediately before executing an instruction that is ...
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10.11 Intelligent I/O Interrupt and CAN Interrupt The intelligent I/O interrupt and CAN interrupt are assigned to ...
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Interrupt Request Register NOTES: 1. See table below for ...
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Interrupt Enable Register NOTES: 1. See table below for bit ...
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11. Watchdog Timer The watchdog timer detects a program which is out of control. The watchdog ...
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Watchdog Timer Control Register Watchdog Timer Start Register ...
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System Clock Control Register NOTES: 1. Rewrite the ...
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12. DMAC This microcomputer contains four DMAC (direct memory access controller) channels that allow data to be ...
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DMAC starts a data transfer by setting the DSR bit in the DMiSL register (i=0 to ...
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DMAi Request Factor Select Register NOTES: 1. Change the DSEL4 ...
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Table 12.2 DMiSL Register ( Function Setting Value ...
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DMA Mode Register NOTES: 1. Use the LDC instruction ...
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DMAi Transfer Count Register b15 b8 b7 NOTES: 1. When the DCTi register to "0000 2. ...
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DMAi Memory Address Register b23 b16 b15 NOTES: 1. When the RWk bit (k ...
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12.1 Transfer Cycles Transfer cycle contains a bus cycle to read data from a memory or ...
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(1) When 8-bit data is transferred or when 16-bit data is transferred from an even source address ...
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12.2 DMAC Transfer Cycles The number of DMAC transfer cycle can be calculated as follows. Any ...
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When DMA transfer request signals are applied to INT0 and INT1 simultaneously and a DMA transfer with ...
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13. DMAC II The DMAC II performs memory-to-memory transfer, immediate data transfer and calculation transfer, which ...
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Exit Priority Register NOTES: 1. The microcomputer exits stop or ...
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13.1.2 DMAC II Index The DMAC II index is a data table which comprises 8 to ...
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Table 13.2 DMAC II Index Configuration in Transfer Mode Memory-to-Memory Transfer /Immediate Data Transfer Chained Transfer Not ...
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13.1.3 Interrupt Control Register for the Peripheral Function For the peripheral function interrupt activating a DMAC ...
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13.3.2 Immediate Data Transfer The DMAC II transfers immediate data to a desired memory location. A fixed ...
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13.4.4 Chained Transfer The CHAIN bit in MOD selects the chained transfer. The following process initiates ...
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13.5 Execution Time DMAC II execution cycle is calculated by the following equations: Multiple transfers ...
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14. Timer The microcomputer has eleven 16-bit timers. Five timers A and six timers B have ...
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Main clock, PLL clock or On-chip clock 1/2n CST (Note ...
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14.1 Timer A Figure 14.3 shows a block diagram of the timer A. Figures 14.4 to 14.7 ...
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Timer Ai Register (i b15 ...
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Timer Ai Mode Register (i Count Start Flag ...
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(1) Up/Down Flag NOTES: 1. Use the MOV instruction to ...
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Trigger Select Register NOTES: 1. Overflow or underflow. Count Source ...
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Table 14.1 Pin Settings for Output from TAi Pin PS1, PS2 Registers OUT (1) P7 /TA0 PS1_0= ...
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14.1.1 Timer Mode In timer mode, the timer counts an internally generated count source (see Table 14.3). ...
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Timer Ai Mode Register (i (Timer Mode ...
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14.1.2 Event Counter Mode In event counter mode, the timer counts how many external signals are applied ...
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Table 14.5 Specifications in Event Counter Mode (when processing two-phase pulse signal on timer A2, A3 and ...
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Timer Ai Mode Register (i (Event Counter Mode ...
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14.1.2.1 Counter Reset by Two-Phase Pulse Signal Processing The timer counter is reset to "0" ...
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14.1.3 One-shot Timer Mode In one-shot timer mode, the timer operates only once for each trigger (see ...
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Timer Ai Mode Register (i (One-Shot Timer Mode ...
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14.1.4 Pulse Width Modulation Mode In pulse width modulation mode, the timer outputs pulse of desired width ...
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Timer Ai Mode Register (i (Pulse Width Modulator Mode ...
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When the reload register is set to "0003 trigger (rising edge of input signal to the TAi ...
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14.2 Timer B Figure 14.16 shows a block diagram of the timer B. Figures 14.17 to ...
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Timer Bi Mode Register (i NOTES: 1. Only ...
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Timer B3, B4,B5 Count Start Flag Figure 14.19 TBSR ...
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14.2.1 Timer Mode In timer mode, the timer counts an internally generated count source (see Table 14.9). ...
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14.2.2 Event Counter Mode In event counter mode, the timer counts how many external signals are ...
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Timer Bi Mode Register (i (Event Counter Mode ...
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14.2.3 Pulse Period/Pulse Width Measurement Mode In pulse period/pulse width measurement mode, the timer measures pulse ...
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Timer Bi Mode Register (i (Pulse Period / Pulse Width Measurement Mode ...
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Count source “H” Pulse to be measured “L” Counter to reload register transfer timing Timing that ...
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15. Three-Phase Motor Control Timer Functions Three-phase motor driving waveform can be output by using the ...
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Table 15.2 Pin Settings Pin PS1, PS2 Registers ...
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Figure 15.1 Three-Phase Motor Control Timer Functions Block Diagram Page 163 ...
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Three-Phase PWM Control Register NOTES: 1. Set the ...
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Three-Phase PWM Control Register NOTES: 1. Rewrite the ...
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Three-Phase Output Buffer Register NOTES: 1. Values of ...
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Timer B2 Interrupt Generation Frequency Set Counter b7 NOTES: 1. Use the MOV instruction to set ...
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Timer B2 Register b15 NOTES: 1. Use a 16-bit data for read and ...
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Timer Ai Mode Register NOTES: 1. ...
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The three-phase control timer function is available by setting the INV02 bit in the INVC0 register ...
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Sawtooth Waveform as a Carrier Wave Sawtooth Wave Signal Wave Timer B2 Timer A4 Start (1) ...
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16. Serial I/O Serial I/O consists of five channels (UART0 to UART4). Each UARTi (i ...
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RxD Polarity RxDi Switching Circuit Selecting Clock Source 00 CKDIR f 1 Inside ...
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UARTi Transmit Buffer Register b15 b8 b7 NOTES: 1. Use the MOV instruction to set the UiTB ...
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UARTi Baud Rate Register b7 NOTES: 1. Use the MOV instruction to set the UiBRG register. 2. ...