M30833FJFP#U5 Renesas Electronics America, M30833FJFP#U5 Datasheet - Page 250

• Manufacturer Part Number: M30833FJFP#U5
• Description: IC M32C/83 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJFP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
. v
3
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Table 17.1 A/D Converter Specifications
NOTES:
Table 19.2 Difference between A/D0 and A/D1
NOTES:
0
2
A/D Conversion Method
Analog Input Voltage
Operating Clock, Ø
Resolution
Operating Mode
Analog Input Pins
A/D Conversion Start Condition
Conversion Rate Per Pin
Analog Input Pins
Extended Analog Input Pins
External Op-Amp
Intelligent I/O used as a Trigger
1
9
C
1. Analog input voltage is not affected by the sample and hold function status.
2. Ø
3. AV
1. When the ADS bit in the AD0CON2 register is set to "0" (channel replacement disabled)
3 .
B
8 /
0
1
Ø
0
3
AD
3
AD
J
Without the sample and hold function, the Ø
With the sample and hold function, the Ø
and ANEX1)
G
4
CC
a
0 -
n
o r
frequency must be under 10 MHz when V
frequency must be under 16 MHz when V
3 .
= V
1
u
, 1
3
p
Item
1
REF
2
(
Item
0
M
0
3
(3)
(1)
6
= V
(1)
2
AD (2)
C
(1)
CC
Page 225
V
8 /
CC
, A/D input voltage (for AN
, 3
.
M
3
2
C
f o
8 /
Successive approximation (with a capacitive coupling amplifier)
0V to AV
f
Select from 8 bits or 10 bits
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
repeat sweep mode 1
34 pins
Software trigger
• The ADST bit in the ADiCON0 (i=0, 1) register is set to "1" (A/D conversion
• The PST bit in the AD0CON2 register is set to "1" (A/D0 and A/D1 start a
External trigger (re-trigger is enabled)
Hardware trigger (re-trigger is enabled)
• Without the sample and hold function
• With the sample and hold function
4
AD
• The timer B2 interrupt request of the three-phase motor control timer functions
When a falling edge is applied to the AD
One of the following interrupt requests is generated after the ADST bit is set to
3
8 pins each for AN (AN
AN15 (AN15
2 extended input pins (ANEX0 and ANEX1)
started) by program
program
"1" by program:
• The intelligent I/O interrupt request
8
conversion simultaneously) by program
(after the ICTB2 counter completes counting)
8-bit resolution : 49 Ø
10-bit resolution : 59 Ø
8-bit resolution : 28 Ø
10-bit resolution : 33 Ø
8
) T
, f
Channel 1 in the group 2 (A/D0), channel 1 in the group 3 (A/D1)
AN (AN
ANEX0, ANEX1
Enabled
Channel 1 in group 2
AD
/2, f
CC
0
AD
(V
to AN
A/D0
AD
/3, f
0
CC
to AN15
CC
0
CC
AD
frequency must be 1 MHz or more.
)
AD
to AN
7
=3.3V.
=5V.
)
frequency must be 250 kHz or more.
/4
7
7
AD
AD
0
, AN0
)
AD
AD
to AN
cycles
cycles
cycles
cycles
0
7
to AN0
Specification
), AN0 (AN0
Select from AN0 (AN0
AN2 (AN2
Not provided
Disabled
Channel 1 in group 3
__________
7
, AN2
TRG
0
pin after the ADST bit is set to "1" by
0
to AN2
0
to AN0
to AN2
7
) or AN15 (AN15
7
7
A/D1
), AN2 (AN2
, AN15
0
to AN0
0
to AN15
17. A/D Converter
7
),
0
to AN2
0
to AN15
7
, ANEX0
7
),
7
)