M30833FJFP#U5 Renesas Electronics America, M30833FJFP#U5 Datasheet - Page 218

• Manufacturer Part Number: M30833FJFP#U5
• Description: IC M32C/83 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJFP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
3
. v
J
Figure 16.17 Serial Data Logic Inverse
2
Figure 16.16 Transfer Format
0
16.2.2 Selecting LSB First or MSB First
1
C
16.2.3 Serial Data Logic Inverse
9
3 .
B
As shown in Figure 16.16, the UFORM bit in the UiC0 register (i=0 to 4) determines data transfer format.
This function is available for 8-bit transfer data.
8 /
After the UiLCH bit in the UiC1 register is set to "1", data logic is inversed when writing to the UiTB register
(i=0 to 4) and reading from the UiRB register. Figure 16.17 shows a switching example of the serial data
logic.
0
1
3
0
3
J
G
(1) When the UFORM Bit in the UiC0 Register (i=0 to 4) is set to "0" (LSB first)
4
a
0 -
n
o r
3 .
1
u
NOTES:
Transfer Clock
Transfer Clock
, 1
3
NOTES:
(2) When the UFORM Bit in the UiC0 Register is set to "1" (MSB first)
(2) When the UiLCH bit in the UiC1 register = 1 (inverse)
(1) When the UiLCH bit in the UiC1 register (i=0 to 4) = 0 (no inverse)
p
1
1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is
1. The above applies to when the UFORM bit in the UiC0 register is set to "0" (LSB first),
2
(
M
(no inverse)
transmitted on the falling edge of the transfer clock and received on the rising edge)
and the UiLCH bit in the UiC1 register is set to "0" (no inverse).
0
the STPS bit in the UiMR bit is set to "0" (1 stop bit) and the PRYE bit is set to "1" (parity enabled).
0
3
(inverse)
6
2
C
TxD
TxD
Page 193
8 /
, 3
i
i
CLKi
RxD
CLKi
TxD
RxD
TxD
“H”
“H”
“H”
“H”
“L”
“L”
“L”
“L”
M
3
i
i
i
i
2
C
f o
8 /
4
3
8
ST
ST
) T
8
ST
ST
ST
ST
D
D
0
0
D
D
D
D
0
0
7
7
D
D
1
1
D
D
D
D
1
1
6
6
D
D
2
2
D
D
D
D
2
2
5
5
D
D
3
3
D
D
D
D
3
3
4
4
D
D
4
4
D
D
D
D
4
4
3
3
D
D
5
5
D
D
D
D
5
5
2
2
D
D
6
6
D
D
D
D
6
6
1
1
D
D
7
7
D
D
D
D
7
7
0
0
P
P
P
P
P
P
SP
SP
ST : Start bit
P : Parity bit
SP : Stop bit
SP
SP
SP
SP
16. Serial I/O (UART)