PIC16F526-I/P Microchip Technology, PIC16F526-I/P Datasheet - Page 44

IC PIC MCU FLASH 1KX12 14DIP

PIC16F526-I/P

Manufacturer Part Number
PIC16F526-I/P
Description
IC PIC MCU FLASH 1KX12 14DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets

Specifications of PIC16F526-I/P

Program Memory Type
FLASH
Program Memory Size
1.5KB (1K x 12)
Package / Case
14-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
11
Ram Size
67 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 3x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
67 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 3 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162096 - HEADER MPLAB ICD2 PIC16F526 8/14
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC16F526
REGISTER 8-1:
DS41326E-page 44
bit 7
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1: Refer to the “PIC16F526 Memory Programming Specification”, DS41317 to determine how to access the
CPDF
2: DRT length (18 ms or 1 ms) is a function of Clock mode selection. It is the responsibility of the application
Configuration Word.
designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in
acceptable operation. Refer to Section 14.1 “DC Characteristics: PIC16F526 (Industrial)” and
Section 14.2 “DC Characteristics: PIC16F526 (Extended)” for V
for this mode of operation.
CPDF: Code Protection bit – Flash Data Memory
1 = Code protection off
0 = Code protection on
IOSCFS: Internal Oscillator Frequency Select bit
1 = 8 MHz INTOSC frequency
0 = 4 MHz INTOSC frequency
MCLRE: Master Clear Enable bit
1 = RB3/MCLR pin functions as MCLR
0 = RB3/MCLR pin functions as RB3, MCLR internally tied to V
CP: Code Protection bit – User Program Memory
1 = Code protection off
0 = Code protection on
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
FOSC<2:0>: Oscillator Selection bits
000 = LP oscillator and 18 ms DRT
001 = XT oscillator and 18 ms DRT
010 = HS oscillator and 18 ms DRT
011 = EC oscillator with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT
100 = INTRC with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT
101 = INTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1 ms DRT
110 = EXTRC with RB4 function on RB4/OSC2/CLKOUT and 1 ms DRT
111 = EXTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1 ms DRT
IOSCFS
CONFIG: CONFIGURATION WORD REGISTER
MCLRE
CP
WDTE
FOSC2
DD
DD
rise time and stability requirements
 2010 Microchip Technology Inc.
(1)
(1)
FOSC1
(1)
(1)
(1)
FOSC0
bit 0

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