SAF-XE167G-72F66L AC Infineon Technologies, SAF-XE167G-72F66L AC Datasheet - Page 97
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SAF-XE167G-72F66L AC
Manufacturer Part Number
SAF-XE167G-72F66L AC
Description
IC MCU 16BIT FLASH PG-LQFP-144
Manufacturer
Infineon Technologies
Series
XE16xr
Datasheet
1.SAF-XE167K-96F66L_AC.pdf
(122 pages)
Specifications of SAF-XE167G-72F66L AC
Core Processor
C166SV2
Core Size
16-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
I²S, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
576KB (576K x 8)
Program Memory Type
FLASH
Ram Size
50K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
118
Number Of Timers
11
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
FXE167G72F66LACXP
SAF-XE167G-72F66LACIN
SP000363815
SAF-XE167G-72F66LACIN
SP000363815
Direct Drive
When direct drive operation is selected (SYSCON0.CLKSEL = 11
derived directly from the input clock signal CLKIN1:
f
The frequency of
times of
Selecting Bypass Operation from the XTAL1
in a similar configuration.
Prescaler Operation
When prescaler operation is selected (SYSCON0.CLKSEL = 10
1
XTAL1) or from the internal clock source through the output prescaler K1 (= K1DIV+1):
f
If a divider factor of 1 is selected, the frequency of
this case the high and low times of
clock
The lowest system clock frequency results from selecting the maximum value for the
divider factor K1:
f
Phase Locked Loop (PLL)
When PLL operation is selected (SYSCON0.CLKSEL = 10
the on-chip phase locked loop is enabled and provides the system clock. The PLL
multiplies the input frequency by the factor F (
F is calculated from the input divider P (= PDIV+1), the multiplication factor N (=
NDIV+1), and the output divider K2 (= K2DIV+1):
(F = N / (P × K2)).
The input clock can be derived either from an external source at XTAL1 or from the on-
chip clock source.
The PLL circuit synchronizes the system clock to the input clock. This synchronization is
performed smoothly so that the system clock frequency does not change abruptly.
Adjustment to the input clock continuously changes the frequency of
locked to
of individual TCSs.
1) Voltages on XTAL1 must comply to the core supply voltage
Data Sheet
SYS
SYS
SYS
B
), the system clock is derived either from the crystal oscillator (input clock signal
=
=
=
f
f
f
f
OSC
IN
OSC
OSC
f
.
SYS
f
(external or internal).
IN
/ K1.
/ 1024.
. The slight variation causes a jitter of
are determined by the duty cycle of the input clock
f
SYS
is the same as the frequency of
f
SYS
are determined by the duty cycle of the input
95
1)
input and using a divider factor of 1 results
f
SYS
V
f
=
DDI1
SYS
f
SYS
f
IN
.
which in turn affects the duration
f
× F).
IN
equals the frequency of
XE166 Family Derivatives
. In this case the high and low
B
, PLLCON0.VCOBY = 0
f
B
Electrical Parameters
IN
, PLLCON0.VCOBY =
B
.
), the system clock is
f
SYS
V2.1, 2008-08
so that it is
XE167x
f
OSC
. In
B
),