SAF-XE167G-72F66L AC Infineon Technologies, SAF-XE167G-72F66L AC Datasheet - Page 115
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SAF-XE167G-72F66L AC
Manufacturer Part Number
SAF-XE167G-72F66L AC
Description
IC MCU 16BIT FLASH PG-LQFP-144
Manufacturer
Infineon Technologies
Series
XE16xr
Datasheet
1.SAF-XE167K-96F66L_AC.pdf
(122 pages)
Specifications of SAF-XE167G-72F66L AC
Core Processor
C166SV2
Core Size
16-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
I²S, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
576KB (576K x 8)
Program Memory Type
FLASH
Ram Size
50K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
118
Number Of Timers
11
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
FXE167G72F66LACXP
SAF-XE167G-72F66LACIN
SP000363815
SAF-XE167G-72F66LACIN
SP000363815
Table 34
Parameter
Master Mode Timing
Slave select output SELO active
to first SCLKOUT transmit edge
Slave select output SELO inactive
after last SCLKOUT receive edge
Transmit data output valid time
Receive data input setup time to
SCLKOUT receive edge
Data input DX0 hold time from
SCLKOUT receive edge
Slave Mode Timing
Select input DX2 setup to first
clock input DX1 transmit edge
Select input DX2 hold after last
clock input DX1 receive edge
Data input DX0 setup time to
clock input DX1 receive edge
Data input DX0 hold time from
clock input DX1 receive edge
Data output DOUT valid time
1) The maximum value further depends on the settings for the slave select output leading delay.
2)
3) The maximum value depends on the settings for the slave select output trailing delay and for the shift clock
4) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and
Data Sheet
t
output delay.
receive data input (bits DXnCR.DSEN = 0).
SYS
= 1/
f
SYS
(= 12.5ns @ 80 MHz)
SSC Master/Slave Mode Timing for Lower Voltage Range
(Operating Conditions apply),
Symbol
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
10
11
12
13
14
CC
CC
CC
SR
SR
SR
SR
SR
SR
CC
113
Min.
0
0.5 ×
t
-13
48
-11
12
8
12
8
11
BIT
C
L
= 50 pF
Values
Typ.
–
–
–
–
–
–
–
–
–
–
XE166 Family Derivatives
Max.
1)
3)
16
–
–
–
–
–
–
44
Electrical Parameters
Unit Note /
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V2.1, 2008-08
Test Co
ndition
2)
2)
4)
7)
7)
7)
7)
XE167x