SAF-XE167G-72F66L AC Infineon Technologies, SAF-XE167G-72F66L AC Datasheet - Page 12
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SAF-XE167G-72F66L AC
Manufacturer Part Number
SAF-XE167G-72F66L AC
Description
IC MCU 16BIT FLASH PG-LQFP-144
Manufacturer
Infineon Technologies
Series
XE16xr
Datasheet
1.SAF-XE167K-96F66L_AC.pdf
(122 pages)
Specifications of SAF-XE167G-72F66L AC
Core Processor
C166SV2
Core Size
16-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
I²S, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
576KB (576K x 8)
Program Memory Type
FLASH
Ram Size
50K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
118
Number Of Timers
11
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
FXE167G72F66LACXP
SAF-XE167G-72F66LACIN
SP000363815
SAF-XE167G-72F66LACIN
SP000363815
Notes to Pin Definitions
1. Ctrl.: The output signal for a port pin is selected by bitfield PC in the associated
2. Type: Indicates the pad type used (St=standard pad, Sp=special pad, DP=double
Table 4
Pin
3
4
5
6
7
Data Sheet
register Px_IOCRy. Output O0 is selected by setting the respective bitfield PC to
1x00
Output signal OH is controlled by hardware.
pad, In=input pad, PS=power supply) and its power supply domain (A, B, M, 1).
Symbol
TESTM
P7.2
EMUX0
TxDC4
CCU62_
CCPOS0A
TDI_C
P8.4
CCU60_
COUT61
TMS_D
TRST
P8.3
CCU60_
COUT60
TDI_D
B
, output O1 is selected by 1x01
Pin Definitions and Functions
Ctrl.
I
O0 / I St/B
O1
O2
I
I
O0 / I St/B
O1
I
I
O0 / I St/B
O1
I
Type Function
In/B
St/B
St/B
St/B
St/B
St/B
St/B
In/B
St/B
St/B
Testmode Enable
Enables factory test modes, must be held HIGH for
normal operation (connect to
An internal pullup device will hold this pin high
when nothing is driving it.
Bit 2 of Port 7, General Purpose Input/Output
External Analog MUX Control Output 0 (ADC1)
CAN Node 4 Transmit Data Output
CCU62 Position Input 0
JTAG Test Data Input
Bit 4 of Port 8, General Purpose Input/Output
CCU60 Channel 1 Output
JTAG Test Mode Selection Input
Test-System Reset Input
For normal system operation, pin TRST should be
held low. A high level at this pin at the rising edge
of PORST activates the XE167’s debug system. In
this case, pin TRST must be driven low once to
reset the debug system.
An internal pulldown device will hold this pin low
when nothing is driving it.
Bit 3 of Port 8, General Purpose Input/Output
CCU60 Channel 0 Output
JTAG Test Data Input
B
, etc.
10
XE166 Family Derivatives
General Device Information
V
DDPB
).
V2.1, 2008-08
XE167x