SAF-XE167G-72F66L AC Infineon Technologies, SAF-XE167G-72F66L AC Datasheet - Page 105
![IC MCU 16BIT FLASH PG-LQFP-144](/photos/12/23/122331/saf-xe167g-72f66l_ac_sml.jpg)
SAF-XE167G-72F66L AC
Manufacturer Part Number
SAF-XE167G-72F66L AC
Description
IC MCU 16BIT FLASH PG-LQFP-144
Manufacturer
Infineon Technologies
Series
XE16xr
Datasheet
1.SAF-XE167K-96F66L_AC.pdf
(122 pages)
Specifications of SAF-XE167G-72F66L AC
Core Processor
C166SV2
Core Size
16-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
I²S, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
576KB (576K x 8)
Program Memory Type
FLASH
Ram Size
50K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
118
Number Of Timers
11
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
FXE167G72F66LACXP
SAF-XE167G-72F66LACIN
SP000363815
SAF-XE167G-72F66LACIN
SP000363815
Table 29
Parameter
Output valid delay for:
RD, WR(L/H)
Output valid delay for:
BHE, ALE
Output valid delay for:
A23 … A16, A15 … A0 (on P0/P1)
Output valid delay for:
A15 … A0 (on P2/P10)
Output valid delay for:
CS
Output valid delay for:
D15 … D0 (write data, MUX-mode)
Output valid delay for:
D15 … D0 (write data, DEMUX-
mode)
Output hold time for:
RD, WR(L/H)
Output hold time for:
BHE, ALE
Output hold time for:
A23 … A16, A15 … A0 (on P2/P10)
Output hold time for:
CS
Output hold time for:
D15 … D0 (write data)
Input setup time for:
READY, D15 … D0 (read data)
Input hold time for:
READY, D15 … D0 (read data)
1) Read data are latched with the same internal clock edge that triggers the address change and the rising edge
Data Sheet
of RD. Address changes before the end of RD have no impact on (demultiplexed) read cycles. Read data can
change after the rising edge of RD.
External Bus Cycle Timing for Upper Voltage Range
(Operating Conditions apply)
1)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
11
12
13
14
15
16
20
21
23
24
25
30
31
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
SR
SR
103
Min.
–
–
–
–
–
–
–
0
0
0
0
0
18
-4
Typ.
Limits
XE166 Family Derivatives
Electrical Parameters
Max.
13
13
14
14
13
14
14
8
8
8
8
8
–
–
Unit Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V2.1, 2008-08
XE167x