SAF-XE167G-72F66L AC Infineon Technologies, SAF-XE167G-72F66L AC Datasheet - Page 93
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SAF-XE167G-72F66L AC
Manufacturer Part Number
SAF-XE167G-72F66L AC
Description
IC MCU 16BIT FLASH PG-LQFP-144
Manufacturer
Infineon Technologies
Series
XE16xr
Datasheet
1.SAF-XE167K-96F66L_AC.pdf
(122 pages)
Specifications of SAF-XE167G-72F66L AC
Core Processor
C166SV2
Core Size
16-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
I²S, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
576KB (576K x 8)
Program Memory Type
FLASH
Ram Size
50K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
118
Number Of Timers
11
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
FXE167G72F66LACXP
SAF-XE167G-72F66LACIN
SP000363815
SAF-XE167G-72F66LACIN
SP000363815
4.5
The XE167 is delivered with all Flash sectors erased and with no protection installed.
The data retention time of the XE167’s Flash memory (i.e. the time after which stored
data can still be retrieved) depends on the number of times the Flash memory has been
erased and programmed.
Note: These parameters are not subject to production test but verified by design and/or
Table 23
Parameter
Programming time per
128-byte page
Erase time per
sector/page
Data retention time
Flash erase endurance for
user sectors
Flash erase endurance for
security pages
Drain disturb limit
1) Programming and erase times depend on the internal Flash clock source. The control state machine needs a
2) A maximum of 64 Flash sectors can be cycled 15,000 times. For all other sectors the limit is 1,000 cycles.
3) This parameter limits the number of subsequent programming operations within a physical sector. The drain
Access to the XE167 Flash modules is controlled by the IMB. Built-in prefetch
mechanisms optimize the performance for sequential access.
Flash access waitstates only affect non-sequential access. Due to prefetch
mechanisms, the performance for sequential access (depending on the software
structure) is only partially influenced by waitstates.
Data Sheet
few system clock cycles. This requirement is only relevant for extremely low system frequencies.
In the XE167 erased areas must be programmed completely (with actual code/data or dummy values) before
that area is read.
disturb limit is applicable if wordline erase is used repeatedly. For normal sector erase/program cycles this
limit will not be violated.
characterization.
Flash Memory Parameters
2)
Flash Characteristics
(Operating Conditions apply)
Symbol
t
t
t
N
N
N
PR
ER
RET
ER
SEC
DD
Min.
–
–
20
15,000 –
10
64
91
Limit Values
Typ.
3
4
–
–
–
1)
1)
–
–
–
Max.
3.5
5
–
XE166 Family Derivatives
Unit
ms
ms
years
cycles Data retention
cycles Data retention
cycles
Electrical Parameters
Note / Test
Condition
ms
ms
1,000 erase /
program
cycles
time 5 years
time 20 years
3)
V2.1, 2008-08
XE167x