SAF-XE167G-72F66L AC Infineon Technologies, SAF-XE167G-72F66L AC Datasheet - Page 44
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SAF-XE167G-72F66L AC
Manufacturer Part Number
SAF-XE167G-72F66L AC
Description
IC MCU 16BIT FLASH PG-LQFP-144
Manufacturer
Infineon Technologies
Series
XE16xr
Datasheet
1.SAF-XE167K-96F66L_AC.pdf
(122 pages)
Specifications of SAF-XE167G-72F66L AC
Core Processor
C166SV2
Core Size
16-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
I²S, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
576KB (576K x 8)
Program Memory Type
FLASH
Ram Size
50K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
118
Number Of Timers
11
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
FXE167G72F66LACXP
SAF-XE167G-72F66LACIN
SP000363815
SAF-XE167G-72F66LACIN
SP000363815
With this hardware most XE167 instructions can be executed in a single machine cycle
of 12.5 ns with an 80-MHz CPU clock. For example, shift and rotate instructions are
always processed during one machine cycle, no matter how many bits are shifted. Also,
multiplication and most MAC instructions execute in one cycle. All multiple-cycle
instructions have been optimized so that they can be executed very fast; for example, a
32-/16-bit division is started within 4 cycles while the remaining cycles are executed in
the background. Another pipeline optimization, the branch target prediction, eliminates
the execution time of branch instructions if the prediction was correct.
The CPU has a register context consisting of up to three register banks with 16 word-
wide GPRs each at its disposal. One of these register banks is physically allocated within
the on-chip DPRAM area. A Context Pointer (CP) register determines the base address
of the active register bank accessed by the CPU at any time. The number of these
register bank copies is only restricted by the available internal RAM space. For easy
parameter passing, a register bank may overlap others.
A system stack of up to 32 Kwords is provided for storage of temporary data. The system
stack can be allocated to any location within the address space (preferably in the on-chip
RAM area); it is accessed by the CPU with the stack pointer (SP) register. Two separate
SFRs, STKOV and STKUN, are implicitly compared with the stack pointer value during
each stack access to detect stack overflow or underflow.
The high performance of the CPU hardware implementation can be best utilized by the
programmer with the highly efficient XE167 instruction set. This includes the following
instruction classes:
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The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
Data Sheet
Standard Arithmetic Instructions
DSP-Oriented Arithmetic Instructions
Logical Instructions
Boolean Bit Manipulation Instructions
Compare and Loop Control Instructions
Shift and Rotate Instructions
Prioritize Instruction
Data Movement Instructions
System Stack Instructions
Jump and Call Instructions
Return Instructions
System Control Instructions
Miscellaneous Instructions
42
XE166 Family Derivatives
Functional Description
V2.1, 2008-08
XE167x