R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 929

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 19.3 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and
it can be read from or written to by the CPU at all times.
Table 19.3 Relationships between N Setting in BRR and Bit Rate B
[Legend]
B:
N:
Pφ:
n and S: Determined by the SMR settings shown in the following table.
Mode
Asynchronous
mode
Clocked synchronous mode
Smart card interface mode
CKS1
0
0
1
1
Bit Rate Register (BRR)
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
SMR Setting
CKS0
0
1
0
1
ABCS Bit Bit Rate
0
1
N =
N =
N =
N =
n
0
1
2
3
64 × 2
32 × 2
8 × 2
S × 2
Pφ × 10
Pφ × 10
Pφ × 10
Pφ × 10
2n – 1
2n + 1
2n – 1
2n – 1
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
× B
6
6
6
6
× B
× B
× B
BCP1
0
0
1
1
− 1
− 1
− 1
− 1
Error
Error (%) = {
Error (%) = {
Error (%) =
Rev. 2.00 Sep. 24, 2008 Page 895 of 1468
SMR Setting
{
B × 64 × 2
B × 32 × 2
BCP0
0
1
0
1
B × S × 2
Pφ × 10
Pφ × 10
2n – 1
2n – 1
2n + 1
Pφ × 10
6
6
× (N + 1)
× (N + 1)
× (N + 1)
REJ09B0412-0200
6
S
32
64
372
256
– 1 } × 100
– 1 } × 100
– 1 × 100
}