R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 626

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Data Transfer Controller (DTC)
12.8
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,
the interrupt set as the activation source is generated. These interrupts to the CPU are subject to
CPU mask level and priority level control in the interrupt controller.
12.9
12.9.1
Operation of the DTC can be disabled or enabled using the module stop control register. The
initial setting is for operation of the DTC to be enabled. Register access is disabled by setting the
module stop state. The module stop state cannot be set while the DTC is activated. For details,
refer to section 28, Power-Down Modes.
12.9.2
Transfer information can be located in on-chip RAM. In this case, the RAME bit in SYSCR must
not be cleared to 0.
12.9.3
When the DTC is activated by a DMAC transfer end interrupt, the DTE bit of DMDR is not
controlled by the DTC but its value is modified with the write data regardless of the transfer
counter value and DISEL bit setting. Accordingly, even if the DTC transfer counter value
becomes 0, no interrupt request may be sent to the CPU in some cases.
When the DTC is activated by a DMAC transfer end interrupt, even if DISEL=0, an automatic
clearing of the relevant activation source flag is not automatically cleared by the DTC. Therefore,
write 1 to the DTE bit by the DTC transfer and clear the activation source flag to 0.
12.9.4
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are disabled, multiple activation sources can be set at one time (only at the initial setting) by
writing data after executing a dummy read on the relevant register.
Rev. 2.00 Sep. 24, 2008 Page 592 of 1468
REJ09B0412-0200
Interrupt Sources
Usage Notes
Module Stop State Setting
On-Chip RAM
DMAC Transfer End Interrupt
DTCE Bit Setting