R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 1098

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 21 I
21.5
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK detection, STOP recognition, and arbitration lost. Table 21.3 shows the contents of each
interrupt request.
Table 21.3 Interrupt Requests
When one of the interrupt conditions in table 21.3 is 1 and the I bit in CCR is 0, the CPU executes
interrupt exception handling. Clear the interrupt sources during interrupt exception handling. Note
that the TDRE and TEND bits are automatically cleared to 0 by writing data to ICDRT, and the
RDRF bit is cleared to 0 by reading ICDRR. In particular, the TDRE bit can be set again at the
same time as data are for transmission written to ICDRT, and 1 extra byte can be transmitted if the
TDRE is again cleared to 0.
21.6
This module has a possibility that the high-level period is shortened in the two states described
below.
In master mode,
• When SCL is driven low by the slave device
• When the rising speed of SCL is lowered by the load on the SCL line (load capacitance or
Therefore, this module monitors SCL and communicates bit by bit in synchronization.
Figure 21.18 shows the timing of the bit synchronous circuit, and table 21.4 shows the time when
SCL output changes from low to Hi-Z and the period which SCL is monitored.
Rev. 2.00 Sep. 24, 2008 Page 1064 of 1468
REJ09B0412-0200
Interrupt Request
Transmit Data Empty
Transmit End
Receive Data Full
Stop Recognition
NACK Detection
Arbitration Lost
pull-up resistance)
Interrupt Request
Bit Synchronous Circuit
2
C Bus Interface 2 (IIC2)
Abbreviation
TXI
TEI
RXI
STPI
NAKI
Interrupt Condition
(TDRE = 1) ⋅ (TIE = 1)
(TEND = 1) ⋅ (TEIE = 1)
(RDRF = 1) ⋅ (RIE = 1)
(STOP = 1) ⋅ (STIE = 1)
{(NACKF = 1) + (AL = 1)} ⋅ (NAKIE = 1)