R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 585

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(8)
The EXDMAC is initialized in hardware standby mode and by a reset. EXDMA transfer is not
guaranteed in these cases.
11.8
11.8.1
The EXDMAC priority level control function can be used for the CPU by setting the CPU priority
control register (CPUPCR). For details, see section 7.7, CPU Priority Control Function Over DTC,
DMAC and EXDMAC.
The EXDMAC priority level can be set independently for each channel by the EDMAP2 to
EDMAP0 bits in EDMDR.
The CPU priority level, which corresponds to the priority level of exception handling, can be set
by updating the values of the CPUP2 to CPUP0 bits in CPUPCR with the interrupt mask bit
values.
When the CPUPCE bit in CPUPCR is set to 1 to enable the CPU priority level control and the
EXDMAC priority level is lower than the CPU priority level, the transfer request of the
corresponding channel is masked and the channel activation is disabled. When the priority level of
another channel is the same or higher than the CPU priority level, the transfer request for another
channel is accepted and transfer is enabled regardless of the priority levels of channels.
The CPU priority level control function holds pending the transfer source, which masked the
transfer request. When the CPU priority level becomes lower than the channel priority level by
updating one of them, the transfer request is accepted and transfer starts. The transfer request held
pending is cleared by writing 0 to the DTE bit.
When the CPUPCE bit is cleared to 0, the lowest CPU priority level is assumed.
Transfer End by Hardware Standby Mode and Reset Input
Relationship among EXDMAC and Other Bus Masters
CPU Priority Control Function Over EXDMAC
Rev. 2.00 Sep. 24, 2008 Page 551 of 1468
Section 11 EXDMA Controller (EXDMAC)
REJ09B0412-0200