R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 1106

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 22 A/D Converter
22.3.1
There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown
in table 22.2.
The converted 10-bit data is stored in bits 15 to 6. The lower 6-bit data is always read as 0.
The data bus between the CPU and the A/D converter has a 16-bit width. The data can be read
directly from the CPU. ADDR must not be accessed in 8-bit units and must be accessed in 16-bit
units.
Table 22.2 Analog Input Channels and Corresponding ADDR Registers
Notes: 1. A/D conversion should be not performed on the same channel by multiple units.
Rev. 2.00 Sep. 24, 2008 Page 1072 of 1468
REJ09B0412-0200
Analog
Input
Channel
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Bit
Bit Name
Initial Value
R/W
2. The ADDRA_1 to ADDRD_1 registers for unit 1 are not used.
A/D Data Registers A to H (ADDRA to ADDRH)
15
Unit 0
ADDRA_0 (Unit 0)
ADDRB_0 (Unit 0)
ADDRC_0 (Unit 0)
ADDRD_0 (Unit 0)
ADDRE_0 (Unit 0)*
ADDRF_0 (Unit 0)*
ADDRG_0 (Unit 0)*
ADDRH_0 (Unit 0)*
R
0
14
R
0
13
R
0
12
R
0
A/D Data Register Storing Conversion Result
1
1
1
1
11
R
0
10
R
0
R
9
0
R
8
0
R
7
0
Unit 1*




ADDRE_1 (Unit 1)*
ADDRF_1 (Unit 1)*
ADDRG_1 (Unit 1)*
ADDRH_1 (Unit 1)*
R
6
0
2

R
5
0

R
4
0
1
1
1
1

R
3
0

R
2
0

R
1
0

R
0
0